AX88190AL datasheet(2/49 Pages) ASIX

2 / 49 page

AX88190A

PCMCIA Fast Ethernet MAC Controller

ASIX ELECTRONICS CORPORATION

CONTENTS

1.0 INTRODUCTION ...............................................................................................................................................5

1.1 GENERAL DESCRIPTION: .....................................................................................................................................5

1.2 AX88190A BLOCK DIAGRAM: ............................................................................................................................5

1.3 AX88190A PIN CONNECTION DIAGRAM .............................................................................................................6

2.0 SIGNAL DESCRIPTION....................................................................................................................................7

2.1 PCMCIA BUS INTERFACE SIGNALS GROUP .........................................................................................................7

2.2 EEPROM SIGNALS GROUP .................................................................................................................................8

2.3 MII INTERFACE SIGNALS GROUP ..........................................................................................................................8

2.4 SNI INTERFACE PINS GROUP ................................................................................................................................9

2.5 MODEM INTERFACE PINS GROUP ..........................................................................................................................9

2.6 GENERAL PURPOSE I/O PINS GROUP .....................................................................................................................9

2.7 MISCELLANEOUS PINS GROUP ............................................................................................................................10

2.8 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE .................................................................11

3.0 MEMORY AND I/O MAPPING ......................................................................................................................12

3.1 EEPROM MEMORY MAPPING ..........................................................................................................................12

3.2 ATTRIBUTE MEMORY MAPPING.........................................................................................................................12

3.3 I/O MAPPING....................................................................................................................................................13

3.4 SRAM MEMORY MAPPING ...............................................................................................................................13

4.0 REGISTERS OPERATION..............................................................................................................................14

4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN............................................................................14

4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)...............................................15

4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write) ..........................................16

4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write) .......................................16

4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM.....................................................................17

4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write).......................................17

4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write) ..................................18

4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write) ...............................18

4.3 MAC CORE REGISTERS ....................................................................................................................................19

4.3.1 Command Register (CR) Offset 00H (Read/Write)....................................................................................21

4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)...........................................................................21

4.3.3 Interrupt mask register (IMR) Offset 0FH (Write) ....................................................................................22

4.3.4 Data Configuration Register (DCR) Offset 0EH (Write) ...........................................................................22

4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .....................................................................22

4.3.6 Transmit Status Register (TSR) Offset 04H (Read) ...................................................................................23

4.3.7 Receive Configuration (RCR) Offset 0CH (Write) ....................................................................................23

4.3.8 Receive Status Register (RSR) Offset 0CH (Read) ....................................................................................23

4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)........................................................................................23

4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ..................................................................24

4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ..................................................................24

4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write) .................................................24

4.3.13 Test Register (TR) Offset 15H (Write).....................................................................................................24

4.3.14 General Purpose Input Register (GPI) Offset 18H (Read) ......................................................................24

4.3.15 General Purpose I/O Register (GPIO) Offset 1AH (Read/Write).............................................................25

5.0 PCMCIA DEVICE ACCESS FUNCTIONS ....................................................................................................26

5.1 ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS. .........................................................................................26

5.2 I/O ACCESS FUNCTION FUNCTIONS. ....................................................................................................................26

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