EPM240 datasheet(39/88 Pages) ALTERA

39 / 88 page

Chapter 2: MAX II Architecture

2–31

I/O Structure

Altera Corporation

MAX II Device Handbook

Bus Hold

Each MAX II device I/O pin provides an optional bus-hold feature. The bus-hold

circuitry can hold the signal on an I/O pin at its last-driven state. Since the bus-hold

feature holds the last-driven state of the pin until the next input signal is present, an

external pull-up or pull-down resistor is not necessary to hold a signal level when the

bus is tri-stated.

The bus-hold circuitry also pulls undriven pins away from the input threshold

voltage where noise can cause unintended high-frequency switching. The designer

can select this feature individually for each I/O pin. The bus-hold output will drive

no higher than V

CCIO to prevent overdriving signals. If the bus-hold feature is enabled,

the device cannot use the programmable pull-up option.

The bus-hold circuitry uses a resistor to pull the signal level to the last driven state.

The DC and Switching Characteristics chapter in the MAX II Device Handbook gives the

specific sustaining current for each V

CCIO voltage level driven through this resistor and

overdrive current used to identify the next-driven input level.

The bus-hold circuitry is only active after the device has fully initialized. The bus-hold

circuit captures the value on the pin present at the moment user mode is entered.

Programmable Pull-Up Resistor

Each MAX II device I/O pin provides an optional programmable pull-up resistor

during user mode. If the designer enables this feature for an I/O pin, the pull-up

resistor holds the output to the V

CCIO level of the output pin’s bank.

1 The programmable pull-up resistor feature should not be used at the same time as the

bus-hold feature on a given I/O pin.

Programmable Input Delay

The MAX II IOE includes a programmable input delay that is activated to ensure zero

hold times. A path where a pin directly drives a register, with minimal routing

between the two, may require the delay to ensure zero hold time. However, a path

where a pin drives a register through long routing or through combinational logic

may not require the delay to achieve a zero hold time. The Quartus II software uses

this delay to ensure zero hold times when needed.

MultiVolt I/O Interface

The MAX II architecture supports the MultiVolt I/O interface feature, which allows

MAX II devices in all packages to interface with systems of different supply voltages.

The devices have one set of VCC pins for internal operation (V

CCINT), and up to four

sets for input buffers and I/O output driver buffers (V

CCIO), depending on the number

of I/O banks available in the devices where each set of VCC pins powers one I/O

bank. The EPM240 and EPM570 devices have two I/O banks respectively while the

EPM1270 and EPM2210 devices have four I/O banks respectively.

EPM240 Datasheet(PDF) 39 Page - Altera Corporation

EPM240 Datasheet(HTML) 39 Page - Altera Corporation

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