ILED_var_100% (A) =

SNSHYS

RSNS

ILED_reg (A) =

(VIN_max ± VIN_60%) x delay

2 x L

335

345

355

365

375

385

395

5

10

15

20

25

30

35

68 PH

33 PH

100 PH

INPUT VOLTAGE (V)

50 %

Duty

100 %

Duty

LM3401

www.ti.com

SNVS516C – AUGUST 2007 – REVISED MAY 2013

Figure 22. LED DC current line regulation LED Vf = 7.0V

For most applications, the average LED current will be the highest at the maximum input voltage and lowest at a

duty cycle somewhat greater than 50%. The maximum LED current variation can be estimated as:

(21)

Where VIN_60% is the input voltage corresponding to a duty cycle of 60%. Since the actual input voltage where

minimum LED current occurs varies with the application, this is an approximation. As the duty cycle approaches

100%, the average LED current will approach ILED_PK. The average LED current will be the highest at the point

that 100% duty cycle is reached. In the case that 100% duty cycle can occur, maximum LED current variation is

calculated as:

(22)

PCB LAYOUT

PCB layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess

switching noise, and improper device operation. The following key points should be followed to ensure a quality

layout.

Traces carrying large AC currents should be as wide and short as possible to minimize trace inductance. These

areas, shown as darker regions in Figure 23, are:

•

VIN between the input capacitor and PFET

•

GND between the input capacitor and catch diode

•

The switch node

As shown in Figure 23, place the input capacitor ground as close as possible to the anode of the catch diode.

The VIN side of the input capacitor should be placed close to the top of the PFET.

The CS node (the node connecting the catch diode cathode, inductor, and PFET source) should be kept as small

as possible. This node is one of the main sources for radiated EMI. The SNS and HYS pins are sensitive to

noise. Be sure to route the SNS trace away from the inductor and the switch node, which are sources of noise.

The SNS and HYS resistors should be placed close to their respective pins and grounded close to the GND pin.

An isolated ground area shown as SGND in Figure 23 is recommended for the SNS, HYS, and GND pin

connections. The two ground areas, GND and SGND, should be connected on an inner or bottom layer. This

connection is shown as two vias in Figure 23.

A large, continuous ground plane can also be used, as long as the input capacitor and catch diode ground area

is somewhat isolated.

The HG trace should be kept as short as possible to minimize inductance and gate ringing (See HG and PFET

selection section).

Finally, for accurate current limit sensing, the CS pin and ILIM resistor connections should be made at the PFET

pads, via separate traces.

Copyright © 2007–2013, Texas Instruments Incorporated

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