R3 =

ILIM_PK x RDS(on)

4 PA

IL

500 PA /Div

VCS

10V/Div

10 Ps/DIV

PDmax =

(125°C ± Ta_max)

T

JA

LM3401

SNVS516C – AUGUST 2007 – REVISED MAY 2013

www.ti.com

Increasing RDS(on) will increase power losses and degrade efficiency. FET RDS(on) has a positive temperature

coefficient. At 125°C, the RDS(on) may be as much as 150% higher than the value at 25°C. The Gate capacitance

of the PFET has a direct impact on both PFET transition time and the power dissipation in the LM3401. Most of

the power dissipated in the LM3401 is used to drive the PFET switch. This power can be calculated as follows:

The average amount of gate driver current required during switching (IG) is:

IG = Qg x fSW

(14)

Where Qg is the PFET gate charge.

And the total power dissipated in the IC is:

PD = (Iq x VIN) + (IG x 4.7V)

(15)

Where Iq is typically 1.05 mA and 4.7V is the typical HG voltage.

Maximum power dissipation within the LM3401 is limited by ambient temperature. Use the following equation to

determine maximum allowable power dissipation, or maximum allowable ambient temperature:

(16)

Where

θJA is the typical thermal resistance of 151°C/W. In general, keeping the gate capacitance below 2000 pF

is recommended to keep propagation delay, switching losses, and power losses low. PFETs with very fast rise

times may cause excessive ringing at the HG node when combined with the inductance of a long HG trace. To

reduce this ringing, a small resistor can be added between HG and the PFET gate. A typical value of 10

Ω is

usually sufficient.

CURRENT LIMIT OPERATION

The LM3401 current limit monitors inductor current at each switching cycle. Current is sensed across the RDS(on)

of the PFET at the CS pin. When the PFET current exceeds the current limit threshold, HG is turned off and the

current limit latch is set. In current limit mode, the PFET is held off until the inductor current falls to near zero.

Figure 19. Typical Current Limit Operation

The current limit threshold is adjusted with a setting resistor, shown as R3 in the typical application schematic,

connected from ILIM to the VIN node of the PFET.

An internal 5.5 µA (typical) current sink at the ILIM pin creates a voltage across the setting resistor. This voltage

is compared to the sensed voltage at the CS pin. Current limit is activated and latched when the voltage at the

CS pin drops below the voltage at the ILIM pin.

The current limit setting resistor, R3, can be calculated from the equation below. The minimum current limit

occurs at maximum RDS(on) and minimum IILIM value.

(17)

Where 4 µA is the minimum IILIM value and ILIM_PK is the peak inductor current limit threshold. ILIM_PK should be

set somewhat higher than the maximum LED current, ILED_PK, to avoid false current limit triggering. The

temperature variation of the PFET RDS(on) will result in an equivalent variation in current limit. To ensure that

current limit is not falsely triggered, use the highest RDS(on) value over the temperature range to set the R3 value.

12

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