PDFET_SW =

fSW x ILED x VIN x (Pon + Poff)

2

LM3401

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SNVS516C – AUGUST 2007 – REVISED MAY 2013

LED average DC current and peak inductor current are not affected by the ripple reduction capacitor. However,

LED peak current is reduced and switching frequency may shift slightly.

Any type of capacitor can be used, provided the working voltage rating is sufficient. In general, higher

capacitance and lower ESR will provide more ripple reduction; a typical value greater than 100 nF is

recommended. Smaller capacitance values will be less effective, and large ESR values may actually increase

LED ripple current.

Despite its effectiveness to smooth LED ripple current, there are two notable disadvantages to using a ripple

reduction capacitor.

First, when used, care must be taken to avoid shorting the LED anode to ground. If this occurs, the capacitor will

force a large negative voltage spike at the SNS pin which could damage the IC.

Second, this capacitor will limit the maximum PWM dimming frequency because it takes some additional time to

charge and discharge. Additionally, ceramic capacitors can generate audible noise due to fast voltage changes

during dimming. To reduce audible noise, use the smallest possible case size, use dimming frequencies below

500 Hz, or use a non-ceramic ripple reduction capacitor.

A small bypass capacitor, in the range of 100 pF to 200 pF can also be used to reduce high frequency switching

noise. This is recommended in higher current applications, where switching noise can adversely affect the SNS

or DIM pins. A small capacitor for noise reduction will have little to no effect on the LED ripple current or dimming

but may help solve potential EMI problems.

HG AND PFET SELECTION

When switching, the HG pin swings from VIN (off state) to 4.7V below VIN (typical). As long as the DIM pin is high

and the SNS pin is below the upper threshold, HG will stay low, driving the PFET on.

The PFET should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating (Id),

maximum Gate-Source voltage (VGS), on-resistance (RDS(on)), and Gate capacitance.

The voltage across the PFET in the off state is equal to the sum of the input voltage and the diode forward

voltage. The VDS must therefore be selected to provide some margin beyond this voltage.

Since the peak current through the PFET is equal to the peak current through the inductor, Id must be rated

higher than the maximum ILED_PK. The LM3401 is capable of 100% duty cycle, therefore, the PFET drain current

should be rated to handle ILED_PK continuously. In this case there is no ripple, so IPK = IAVE.

Although the typical HG voltage is VIN - 4.7V, this voltage can go much lower during the initial PFET turn-on time.

How far HG swings at turn-on depends on several factors including the gate capacitance, on-time, and input

voltage. As shown in the Typical Performance Characteristics, the initial HG voltage swing increases with

decreasing PFET gate capacitance. Therefore, A PFET must be selected with a maximum VGS rating larger than

the initial HG voltage. Conversely, when driving PFETs with larger gate capacitance, the initial HG voltage will be

lower. In some cases, a low VGS threshold PFET may be required to ensure complete turn-on. Use the Typical

Performance curve as a guideline to selecting a proper PFET.

Note that HG will eventually settle around the typical voltage of VIN - 4.7V regardless of the PFET gate

capacitance.

HG has an absolute minimum voltage of 1.2V typically. When the input voltage is below approximately 6V, this

minimum limit causes a reduction in drive voltage. At 5V input, for example, HG will swing to 1.2V (or a gate

drive voltage of -3.8V). This may not be sufficient to drive some PFETs, and at this reduced HG voltage, RDS(on)

is likely to increase and trigger current limit. Therefore, a low VGS threshold PFET is also recommended for lower

input voltage applications.

The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are

difficult to precisely calculate, the equations below can be used to estimate total power dissipation, which is the

sum of PDCOND and PDSW.

PDFET_COND = RDS(on) x ILED

2 x D

(12)

(13)

Where Pon = PFET turn-on time, Poff = PFET turn-off time, and D is the duty cycle. A value of 10 ns to 50 ns is

typical for ton and toff. Longer PFET on and off times will degrade both efficiency and accuracy.

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