LM4921

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SNAS178E – JULY 2003 – REVISED MAY 2013

I2S INTERFACE BUS (J2 - See Figure 21 )

The I2S standard provides a uni-directional serial interface designed specifically for digital audio. For the

LM4921, the interface provides access to a 48kHz, 16 bit full-range stereo audio DAC. This interface uses a

three wire system of clock (I2S_CLK), data (I2S_DATA), and word select (I2S_WS, sometimes called Right/Left

Select).

A bit clock (I2S_CLK) at 32 or 64 times the sample frequency is established by the I2S system master and the

word select (I2S_WS) line is driven at a frequency equal to the sampling rate of the audio data, in this case

48kHz. The word line is registered to change on the positive edge of the bit clock. The serial data (I2S_DATA) is

sent MSB first, again registers on the positive edge of the bit clock, delayed by 1 bit clock cycle relative to the

changing of the word line (typical I2S format).

MCLK/XTAL_IN (S1 MCLK SEL - See Figure 21)

This is the input for an external Master Clock. The jumper at S1 must be removed (disconnecting the onboard

crystal from the circuit) when using an external Master Clock.

STEREO HEADPHONE OUTPUT JACK (J3 - See Figure 21)

This is the stereo headphone output. Each channel is single-ended, with 100uF DC output blocking capacitors

mounted on the demo board (C6 and C7). These capacitors are necessary to block the 1/2 VDD DC bias and

prevent it from flowing through the headphone speakers (DC current will destroy most audio speakers) while

allowing the audio ac signal to pass through. The jack features a typical stereo headphone pinout.

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