LM4921

SNAS178E – JULY 2003 – REVISED MAY 2013

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BYPASS CHARGE RATE BIT 12

This control pin allows the user to change the Bypass Capacitor's charge rate by a factor of two. Setting this bit

at zero will set the circuit to it's normal 1x rate. Setting the bit to High will double the charge rate and allow the

part to turn on faster with a slight degradation in turn on click/pop noise.

BITS 5, 13, 14, and 15

Bits 13, 14, and 15 are all reserve bits and must be set to low/zero/ground.

Bit 5 must be set High.

SPI CONTROL INTERFACE BUS (J1)

SPI DATA: This is the serial data pin.

SPI CLK: This is the clock input pin.

SPI ENABLE: This is the SPI enable pin.

SPI TIMING DIAGRAM

SPI OPERATIONAL REQUIREMENTS

1. The maximum clock rate is 5MHz for the CLK pin.

2. CLK must remain logic-high for at least 100ns (tCH ) after the rising edge of CLK, and CLK must remain logic-

low for at least 100ns (tCL ) after the falling edge of CLK.

3. Data bits are written to the DATA pin with the least significant bit (LSB) first.

4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 20ns

(tDS) before the rising edge of CLK. Also, any transition on DATA must occur at least 20ns (tDH) after the rising

edge of CLK and stabilize before the next rising edge of CLK.

5. ENABLE should be logic-high only during serial data transmission.

6. ENABLE must be logic-high at least 20ns (tES ) before the first rising edge of CLK, and ENABLE has to remain

logic-high at least 20ns (tEH ) after the sixteenth rising edge of CLK.

7. If ENABLE remains logic-low for more than 10ns before all 16 bits are transmitted then the data latch will be

aborted.

8. If ENABLE is logic-high for more than 16 CLK pulses then only the first 16 data bits will be latched and

activated at rising edge of sixteenth CLK.

9. ENABLE must remain logic-low for at least 30ns (tEL ).

10. Coincidental rising or falling edges of CLK and ENABLE are not allowed. If CLK is to be held logic-high after

the data transmission, the falling edge of CLK must occur at least 20ns (tCS ) before ENABLE transitions to logic-

high for the next set of data.

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