LM5116-HT

SLVSBS8B – OCTOBER 2013 – REVISED JANUARY 2014

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Absolute Maximum Ratings

(1)

VIN to GND

-0.3 to 80

V

VCC, VCCX, UVLO to GND (2)

-0.3 to 16

V

SW, CS to GND

-3.0 to 80

V

HB to SW

-0.3 to 16

V

HO to SW

-0.3 to HB + 0.3

V

VOUT to GND

-0.3 to 80

V

CSG to GND

-1 to 1

V

LO to GND

-0.3 to VCC + 0.3

V

SS to GND

-0.3 to 7

V

FB to GND

-0.3 to 7

V

DEMB to GND

-0.3 to VCC

V

RT to GND

-0.3 to 7

V

EN to GND

-0.3 to 80

V

ESD Rating

2

kV

HBM (3)

Storage Temperature Range

-55 to 190

°C

Junction Temperature

190

°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed

performance limits and associated test conditions, see the Electrical Characteristics tables.

(2)

These pins must not exceed VIN.

(3)

The human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin. 2 kV rating for all pins except VIN

which is rated for 1.5 kV.

THERMAL INFORMATION

LM5116-HT

THERMAL METRIC(1)

JD

UNITS

20 PINS

θJA

Junction-to-ambient thermal resistance(2)

43.2

θJCtop

Junction-to-case (top) thermal resistance(3)

N/A

θJB

Junction-to-board thermal resistance(4)

21.97

°C/W

ψJT

Junction-to-top characterization parameter(5)

12.95

ψJB

Junction-to-board characterization parameter(6)

18.21

θJCbot

Junction-to-case (bottom) thermal resistance(7)

5.25

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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