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LM8330 Datasheet(PDF) 2 Page - Texas Instruments |
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LM8330 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 54 page ![]() 1 2 3 4 5 A B C D E LM8330 Main processing device ACCESS.bus Command Interpreter Input/Output Expansion SDA SCL RESETN IRQN 1.8V (typ) VCC Internal OSC DIV 32 kHz Reference Clock PWM Generator Key-Scan Control Wake-Up Control Keypad Matrix PWM0 PWM1 PWM2 Input/Output Sleep Control General Purpose Inputs/Outputs NOTE: This diagram illustrates IO configuration 3 with IRQN enabled ASIP ESD Protection 0.1 PF (required) LM8330 SNVS839A – JUNE 2012 – REVISED MARCH 2013 www.ti.com DESCRIPTION (CONTINUED) The LM8330 is available in a 25-bump lead-free DSBGA package size 2.0 mm x 2.0 mm x 0.6 mm (0.4 mm pitch). The LM8330 has integrated ASIP (Application Specific Integrated Passives) on the KPX[7:0] and KPY[10:0] pins. These pins are designed to tolerate IEC61000-4-2 level 4 ESD: ±8 kV direct contact. LM8330 FUNCTION BLOCKS PACKAGE MARKING Figure 1. LM8330 Pinout - Top View (balls underneath) 2 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: LM8330 |
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