LM8330 datasheet(39/54 Pages) TI2

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LM8330

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SNVS839A – JUNE 2012 – REVISED MARCH 2013

GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2

Table 71. GPIOIBE2 - GPIO Interrupt Edge Configuration Register 2

Address

Type

Defines whether an interrupt on KPY[11:8] was triggered on either edge or

GPIOIBE2

0xCE

R/W

on a single edge. See Table 74 for the edge configuration.

Bit - Name

Bit

Default

Bit Function

(reserved

7:4

(reserved)

Interrupt both edges bits for KPY[11:8]:

KPY[11:8]IBE

3:0

0x0

0: interrupt generated at the active edge.

1: interrupt generated after either edge.

GPIOIEV0 - GPIO Interrupt Edge Select Register 0

Table 72. GPIOIEV0 - GPIO Interrupt Edge Select Register 0

Address

Type

GPIOIEV0

0xCF

R/W

Select Interrupt edge for KPX[7:0].

Bit - Name

Bit

Default

Bit Function

Interrupt edge select from KPX[7:0]:

KPX[7:0]EV

7:0

0xFF

0: interrupt at low level or falling edge

1: interrupt at high level or rising edge

GPIOIEV1 - GPIO Interrupt Edge Select Register 1

Table 73. GPIOIEV1 - GPIO Interrupt Edge Select Register 1

Address

Type

GPIOIEV1

0xD0

R/W

Select Interrupt edge for KPY[7:0].

Bit - Name

Bit

Default

Bit Function

Interrupt edge select from KPY[7:0]:

KPY[7:0]EV

7:0

0xFF

0: interrupt at low level or falling edge

1: interrupt at high level or rising edge

GPIOIEV2 - GPIO Interrupt Edge Select Register 2

Table 74. GPIOIEV2 - GPIO Interrupt Edge Select Register 2

Address

Type

GPIOIEV2

0xD1

R/W

Select Interrupt edge for KPY[11:8].

Bit - Name

Bit

Default

Bit Function

(reserved)

7:4

(reserved)

Interrupt edge select from KPY[11:8]:

KPY[11:8]EV

3:0

0xFF

0: interrupt at low level or falling edge

1: interrupt at high level or rising edge

GPIOIE0 - GPIO Interrupt Enable Register 0

Table 75. GPIOIE0 - GPIO Interrupt Enable Register 0

Address

Type

GPIOIE0

0xD2

R/W

Enable/disable interrupts on KPX[7:0].

Bit - Name

Bit

Default

Bit Function

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