0x12

0x02

0

MOSI

(host)

R/W

Addr

Data

(Device 3)

0x01

0xFF

1

R/W

Addr

Data

(Device 2)

0x13

0x50

0

R/W

Addr

Data

(Device 1)

XX

X

XX

XX

X

XX

XX

X

MISO

(host)

0x7F

0xFF

1

R/W

Addr

Data

(Device 3)

0x7F

0xFF

1

R/W

Addr

Data

(Device 2)

0x7F

0xFF

1

R/W

Addr

Data

(Device 1)

0x12

0x02

0

0x01

0x20

1

0x13

0x50

0

48-bit SPI Transaction #1

48-bit SPI Transaction #2

XX

SS

(host)

SCK

(host)

16xN clocks

Device N-1

Read Data

Device 1

Read Data

Device N

Read Data

MOSI

(host)

'21¶7 &$5(

SPI Read Data

16xN clocks

³16x1´

³16x1´

³16x1´

Device N

Read Data

Device N-1

Read Data

Device 1

Read Data

SPI Read Data

MISO

(host)

A6 A5 A4 A3 A2 A1 A0

1

³8x1´

A6 A5 A4 A3 A2 A1

1

A0 D7 D6 D5 D4

D2 D1 D0

D3

LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

www.ti.com

Figure 8. SPI Daisy-Chain Read

SPI Daisy-Chain Read and Write Example

The following example further clarifies LMH0366 SPI daisy-chain operation. Assume a daisy-chain of three

LMH0366 devices (Device 1, Device 2, and Device 3), with Device 1 as the first device in the chain and Device 3

as the last device in the chain, as shown by the first three devices in Figure 6. Since there are three devices in

the daisy-chain, each SPI transaction is 48-bits long.

This example shows an SPI operation combining SPI reads and writes in order to accomplish the following three

tasks:

1. Write 0x02 to register 0x12 of Device 1 in order to set the output swing of both SDO0 and SDO1 to 400 mVP-

P.

2. Read the contents of register 0x01 of Device 2.

3. Write 0x50 to register 0x13 of Device 3 in order to set the output de-emphasis of both SDO0 and SDO1 to 3

dB.

Figure 9 shows the two 48-bit SPI transactions required to complete these tasks (the bits are shifted in left to

right).

Figure 9. SPI Daisy-Chain Read and Write Example

The following occurs at the end of the first transaction:

1. Write 0x02 to register 0x12 of Device 1.

2. Latch the data from register 0x01 of Device 2.

3. Write 0x50 to register 0x13 of Device 3.

In the second transaction, three dummy reads (each consisting of 16 “1”s) are shifted in, and the read data from

Device 2 (with value 0x20) appears on MISO in the 25th through 32nd clock cycles.

18

Submit Documentation Feedback

Copyright © 2012–2013, Texas Instruments Incorporated

Product Folder Links: LMH0366