LMH0366 datasheet(26/41 Pages) TI2

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LMH0366

SNAS585D – APRIL 2012 – REVISED APRIL 2013

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Table 8. SPI Registers (continued)

Addr

Name

Bits

Field

R/W

Default

Description

(hex)

(binary)

Rate Select

7:2

RSVD

R/W

001001

Reserved.

1:0

RATE_SEL

R/W

Rate mode select. Select rate

mode using the following code

(must set register 0x1D bit 0 to

override RATE pins first).

00: Auto-rate detect - video rates

(270, 1483.5, 1485, 2967, 2970

Mbps).

01: 270 Mbps.

10: 1483.5/1485 Mbps,

2967/2970 Mbps.

11: 125 Mbps.

Rate Select Control

7:1

RSVD

R/W

1000000

Reserved.

RATE_SEL_OV

R/W

Rate select override to override

use of RATE pins.

0: No override. Rate mode is

selected by RATE pins.

1: Override rate selection using

(RATE_SEL) instead of using

RATE pins.

Output Select

RSVD

R/W

Reserved.

6:5

SDO0_SEL

R/W

SDO0 manual output selection.

When register 0x09 bit 5 is set

(to override pin mode), this field

allows manual selection of the

SDO0 output.

00: Reclocked data, when

locked; bypassed data, when

unlocked.

01: Bypassed data.

10: Muted.

11: Reclocked data, when

locked; bypassed data, when

unlocked.

4:3

SDO1_SEL

R/W

SDO1 manual output selection.

When register 0x09 bit 5 is set

(to override pin mode), this field

allows manual selection of the

SDO1 output.

00: Recovered clock, when

locked; muted, when unlocked.

01: Reclocked data, when

locked; bypassed data, when

unlocked.

10: Muted.

11: Bypassed data.

2:0

RSVD

R/W

011

Reserved.

Reserved

7:0

RSVD

R/W

01010101

Reserved.

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