BCK

LRCK

DOUT

t(BCKH)

t(BCKL)

t(LRHD)

t(LRCP)

t(LRSU)

t(BCKP)

t(CKDO)

t(LRDO)

1.4 V

1.4 V

0.5 VDD

T0017-02

PCM1808-Q1

SLES265A – MARCH 2011 – REVISED AUGUST 2012

www.ti.com

INTERFACE TIMING

Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively.

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

1/(64 fS)

ns

t(BCKH)

BCK pulse duration, HIGH

1.5 × t(SCKI)

ns

t(BCKL)

BCK pulse duration, LOW

1.5 × t(SCKI)

ns

t(LRSU)

LRCK setup time to BCK rising edge

50

ns

t(LRHD)

LRCK hold time to BCK rising edge

10

ns

t(LRCP)

LRCK period

10

μs

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

40

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

40

ns

tr

Rise time of all signals

20

ns

tf

Fall time of all signals

20

ns

NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Rise and fall times are from 10% to

90% of the input/output signal swing. Load capacitance of DOUT is 20 pF. t(SCKI) is the SCKI period.

Figure 22. Audio Data Interface Timing (Slave Mode: LRCK and BCK Work as Inputs)

16

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