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PCM1808 Datasheet(PDF) 18 Page - Texas Instruments |
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PCM1808 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 29 page ![]() 32/fS T0082-01 48/fin or 48/fS Fade-In Start Fade-In Complete DOUT DOUT (Contents) Normal Data Synchronization Lost Synchronous 1/fS BPZ State of Synchronization Asynchronous Synchronous Resynchronization Synchronization Lost Asynchronous Resynchronization Synchronous Normal Data Undefined Data Normal Data Zero Data Zero Data Normal Data 48/fin or 48/fS Fade-In Restart 32/fS PCM1808-Q1 SLES265A – MARCH 2011 – REVISED AUGUST 2012 www.ti.com SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1808-Q1 operates under LRCK (pin 7), synchronized with system clock SCKI (pin 6). The PCM1808-Q1 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCK/frame (±5 BCKs for 48 BCK/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced to zero data (BPZ code) until resynchronization between LRCK and SCKI is established. In the case of changes less than ±5 BCKs for 64 BCK/frame (±4 BCKs for 48 BCK/frame), resynchronization does not occur and the previously described digital output control and discontinuity do not occur. Figure 25 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, the PCM1808-Q1 can generate some noise in the audio signal. Also, the transition of normal data to undefined data creates a discontinuity in the digital output data, which can generate some noise in the audio signal. The digital output is valid after resynchronization completes and the time of 32/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS until the level corresponding to the analog input signal is obtained. If synchronization is lost during the fade-in or fade-out operation, the operation stops and DOUT (pin 9) is forced to zero data immediately. The fade-in operation resumes from mute after the time of 32/fS following resynchronization. Figure 25. ADC Digital Output for Loss of Synchronization and Resynchronization 18 Copyright © 2011–2012, Texas Instruments Incorporated |
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