BCK

SCKI

t(SCKBCK)

1.4 V

0.5 VDD

T0074-01

t(SCKBCK)

BCK

LRCK

DOUT

t(BCKH)

t(BCKL)

t(CKLR)

t(LRCP)

t(BCKP)

t(CKDO)

t(LRDO)

0.5 VDD

0.5 VDD

0.5 VDD

T0018-02

PCM1808-Q1

www.ti.com

SLES265A – MARCH 2011 – REVISED AUGUST 2012

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t(BCKP)

BCK period

150

1/(64 fS)

2000

ns

t(BCKH)

BCK pulse duration, HIGH

65

1200

ns

t(BCKL)

BCK pulse duration, LOW

65

1200

ns

t(CKLR)

Delay time, BCK falling edge to LRCK valid

–10

20

ns

t(LRCP)

LRCK period

10

1/fS

125

μs

t(CKDO)

Delay time, BCK falling edge to DOUT valid

–10

20

ns

t(LRDO)

Delay time, LRCK edge to DOUT valid

–10

20

ns

tr

Rise time of all signals

20

ns

tf

Fall time of all signals

20

ns

NOTE: Timing measurement reference level is 0.5 VDD. Rise and fall times are from 10% to 90% of the input/output signal

swing. Load capacitance of all signals is 20 pF.

Figure 23. Audio Data Interface Timing (Master Mode: LRCK and BCK Work as Outputs)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

t(SCKBCK)

Delay time, SCKI rising edge to BCK edge

5

30

ns

NOTE: Timing measurement reference level is 1.4 V for input and 0.5 VDD for output. Load capacitance of BCK is 20 pF. This

timing is applied when SCKI frequency is less than 25 MHz.

Figure 24. Audio Clock Interface Timing (Master Mode: BCK Works as Output)

Copyright © 2011–2012, Texas Instruments Incorporated

17