PCM1808-Q1

SLES265A – MARCH 2011 – REVISED AUGUST 2012

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VREF PIN

To ensure low source impedance of the ADC references, 0.1-

μF ceramic and 10-μF electrolytic capacitors are

recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF

pin to reduce dynamic errors on the ADC references.

DOUT PIN

The DOUT pin has a large load-drive capability, but if the DOUT line is long, locating a buffer near the

PCM1808-Q1 and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and

maximize the dynamic performance of the ADC.

SYSTEM CLOCK

The quality of the system clock can influence dynamic performance, as the PCM1808-Q1 operates based on a

system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference

between system clock transition and BCK or LRCK transition in slave mode.

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