Data Sheet

ADPA1112

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 7 of 21

Figure 2. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 6

NIC

No Internal Connection. The NIC pins are not connected internally. For normal operation, connect the NIC pins to ground.

3, 5, 10, 12

GND

Ground. The GND pins must be connected to the RF and the DC ground. See Figure 3 for the interface schematic.

4

RFIN

RF Input. The RFIN pin is AC-coupled and matched to 50Ω. See Figure 4 for the interface schematic.

7

VGG1

Gate Bias for the First and Second Gain Stages. Adjust the negative voltage on the VGG1 pin to set IDQ to the desired level. See

Figure 8 for the interface schematic.

8

VDD1

Drain Bias for the First Gain Stage. Capacitively bypass as shown in the typical application circuit (see Figure 59). See Figure 7 for

the interface schematic.

9

VDET

Detector Diode to Measure the RF Output Power. Used in combination with the VREF pin. The difference in voltage (VREF voltage

(VREF) − VDET voltage (VDET)) is a temperature compensated DC voltage that is proportional to the RF POUT. Connect a 40.2kΩ

resistor between the VDET pin and 5V to provide the DC bias. See Figure 5 for the interface schematic.

11

RFOUT

RF Output. The RFOUT pin is AC-coupled and matched to 50Ω. See Figure 5 for the interface schematic.

13

VREF

Reference Diode for Temperature Compensation of the VDET RF POUT Measurements. Connect a 40.2kΩ resistor between the VREF

pin and 5V to provide DC bias. See Figure 6 for the interface schematic.

14

VDD2

Drain Bias for the Second Gain Stage. Capacitively bypass as shown in the typical application circuit (see Figure 59). See Figure 5 for

the interface schematic.

Package Base

GND

The package base must be connected to the RF and the DC ground. See Figure 3 for the interface schematic.