WAKE

VDD

DONE

RSTn

ttIPt

ttR_EXT + tRSTnt

ttDDONEt

tDONE

trRSTn

tfRSTn

trWAKE

tfWAKE

ttRSTn+tDBt

ttRSTn+ tIPt

DELAY/

M_RST

ttWAKEt

ttM_RST

ttRSTnt

7

TPL5010

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SNAS651A – JANUARY 2015 – REVISED SEPTEMBER 2018

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(1)

Limits are specified by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are specified through

correlations using statistical quality control (SQC) method.

(2)

Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped

production material.

(3)

This parameter is specified by design and/or characterization and is not tested in production.

(4)

In case of RSTn from its falling edge, or in case of WAKE from its rising edge.

7.6 Timing Requirements

MIN(1)

NOM(2)

MAX(1)

UNIT

trRSTn

Rise Time RSTn (3)

Capacitive load 50 pF, Rpullup 100 kΩ

11

µs

tfRSTn

Fall Time RSTn (3)

Capacitive load 50 pF, Rpullup 100 kΩ

50

ns

trWAKE

Rise Time WAKE (3)

Capacitive load 50 pF

50

ns

tfWAKE

Fall Time WAKE (3)

Capacitive load 50 pF

50

ns

tDDONE

DONE to RSTn or WAKE to DONE

delay

Minimum delay(4)

100

ns

Maximum delay (4)

tIP-

20ms

ms

tM_RST

Valid Manual Reset

Observation time 30 ms

20

ms

tDB

De-bounce Manual Reset

20

ms

Figure 1. TPL5010 Timing