ADC1175

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SNAS012H – JANUARY 2000 – REVISED APRIL 2013

CONVERTER ELECTRICAL CHARACTERISTICS (continued)

The following specifications apply for AVDD = DVDD = +5.0VDC, OE = 0V, VRT = +2.6V, VRB = 0.6V, CL = 20 pF, fCLK = 20MHz

at 50% duty cycle. Boldface limits apply for TA = TMIN to TMAX; all other limits TA = 25°C

(1)(2)

Symbol

Parameter

Conditions

Typical(3)

Limits(3)

Units

Power Supply Characteristics

IADD

Analog Supply Current

DVDD = AVDD =5.25V

9.5

mA

IDDD

Digital Supply Current

DVDD = AVDD =5.25V

2.5

mA

DVDD AVDD =5.25V, fCLK = 20 MHz

12

17

mA (max)

IAVDD +

Total Operating Current

DVDD AVDD =5.25V, fCLK = 30 MHz

13

IDVDD

DVDD = AVDD =5.25V, CLK Low

(4)

9.6

mA

DVDD = AVDD =5.25V, fCLK = 20 MHz

60

85

mW (max)

Power Consumption

DVDD = AVDD =5.25V, fCLK = 30 MHz

65

mW

CLK, OE Digital Input Characteristics

VIH

Logical High Input Voltage

DVDD = AVDD = +5.25V

3.0

V (min)

VIL

Logical Low Input Voltage

DVDD = AVDD = +5.25V

1.0

V (max)

IIH

Logical High Input Current

VIH = DVDD = AVDD = +5.25V

5

µA

IIL

Logic Low Input Current

VIL = 0V, DVDD = AVDD = +5.25V

−5

µA

CIN

Logic Input Capacitance

5

pF

Digital Output Characteristics

IOH

High Level Output Current

DVDD = 4.75V, VOH = 2.4V

−1.1

mA (max)

IOL

Low Level Output Current

DVDD = 4.75V, VOL = 0.4V

1.6

mA (min)

DVDD = 5.25V

IOZH,

Tri-State Leakage Current

OE = DVDD, VOL

±20

µA

IOZL

= 0V or VOH = DVDD

AC Electrical Characteristics

fC1

Maximum Conversion Rate

30

20

MHz (min)

fC2

Minimum Conversion Rate

1

MHz

CLK rise to data rising

19.5

ns

tOD

Output Delay

CLK rise to data falling

16

ns

Pipeline Delay (Latency)

2.5

Clock Cycles

tDS

Sampling (Aperture) Delay

CLK low to acquisition of data

3

ns

tAJ

Aperture Jitter

30

ps rms

tOH

Output Hold Time

CLK high to data invalid

10

ns

tEN

OE Low to Data Valid

Loaded as in Figure 18

11

ns

tDIS

OE High to High Z State

Loaded as in Figure 18

15

ns

fIN = 1.31 MHz, VIN = FS - 2 LSB

7.5

fIN = 4.43 MHz, VIN = FS - 2 LSB

7.3

7.0

ENOB

Effective Number of Bits

Bits (min)

fIN = 9.9 MHz, VIN = FS - 2 LSB

7.2

fIN = 4.43 MHz, fCLK = 30 MHz

6.5

fIN = 1.31 MHz, VIN = FS - 2 LSB

46.9

fIN = 4.43 MHz, VIN = FS - 2 LSB

45.7

43

SINAD

Signal-to- Noise & Distortion

dB (min)

fIN = 9.9 MHz, VIN = FS - 2 LSB

45.1

fIN = 4.43 MHz, fCLK = 30 MHz

40.9

fIN = 1.31 MHz, VIN = FS - 2 LSB

47.6

fIN = 4.43 MHz, VIN = FS - 2 LSB

46

44

SNR

Signal-to- Noise Ratio

dB (min)

fIN = 9.9 MHz, VIN = FS - 2 LSB

46.1

fIN = 4.43 MHz, fCLK = 30 MHz

42.1

(4)

At least two clock cycles must be presented to the ADC1175 after power up. See THE ADC1175 CLOCK for details.

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