ADC1175

SNAS012H – JANUARY 2000 – REVISED APRIL 2013

www.ti.com

SPECIFICATION DEFINITIONS

ANALOG INPUT BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz

plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input

signal is the full power bandwidth.

APERTURE JITTER is the time uncertainty of the sampling point (tDS), or the range of variation in the sampling

delay.

BOTTOM OFFSET is the difference between the input voltage that just causes the output code to transition to

the first code and the negative reference voltage. Bottom offset is defined as EOB = VZT - VRB, where VZT is the

first code transition input voltage. Note that this is different from the normal Zero Scale Error.

DIFFERENTIAL GAIN ERROR is the percentage difference between the output amplitudes of a high frequency

reconstructed sine wave at two different d.c. levels.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DIFFERENTIAL PHASE ERROR is the difference in the output phase of a reconstructed small signal sine wave

at two different d.c. levels.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion Ratio, or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is

equivalent to a perfect ADC of this (ENOB) number of bits.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

zero scale (½LSB below the first code transition) through positive full scale (½LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

The end point test method is used.

OUTPUT DELAY is the time delay after the rising edge of the input clock before the data update is present at the

output pins.

OUTPUT HOLD TIME is the length of time that the output data is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output stage. Data for any give sample is available the Pipeline Delay plus the Output Delay

after that sample is taken. New data is available at every clock cycle, but the data lags the conversion by the

pipeline delay.

SAMPLING (APERTURE) DELAY is that time required after the fall of the clock input for the sampling switch to

open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the "hold" mode tDS after

the clock goes low.

SIGNAL TO NOISE RATIO (SNR) is the ratio of the rms value of the input signal to the rms value of the other

spectral components below one-half the sampling frequency, not including harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio of the rms value of the input signal to

the rms value of all of the other spectral components below half the clock frequency, including harmonics but

excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOP OFFSET is the difference between the positive reference voltage and the input voltage that just causes the

output code to transition to full scale and is defined as EOT = VFT − VRT. Where VFT is the full scale transition

input voltage. Note that this is different from the normal Full Scale Error.

TOTAL HARMONIC DISTORTION (THD) is the ratio of the rms total of the first six harmonic components, to the

rms value of the input signal.

12

Submit Documentation Feedback

Copyright © 2000–2013, Texas Instruments Incorporated

Product Folder Links: ADC1175