ADC121S705

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SNAS355B – DECEMBER 2006 – REVISED MARCH 2013

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC121S705:

−40°C ≤ TA ≤ +105°C

+4.5V

≤ VA ≤ +5.5V

1V

≤ VREF ≤ VA

8 MHz

≤ fCLK ≤ 16 MHz

VCM: See Input Common Mode Voltage

POWER CONSUMPTION

The architecture, design, and fabrication process allow the ADC121S705 to operate at conversion rates up to 1

MSPS while consuming very little power. The ADC121S705 consumes the least amount of power while operating

in power down mode. For applications where power consumption is critical, the ADC121S705 should be

operated in power down mode as often as the application will tolerate. To further reduce power consumption,

stop the SCLK while CS is high.

Short Cycling

Another way of saving power is to short cycle the conversion process. This is done by pulling CS high after the

last required bit is received from the ADC121S705 output. This is possible because the ADC121S705 places the

latest converted data bit on DOUT as it is generated. If only 8-bits of the conversion result are needed, for

example, the conversion can be terminated by pulling CS high after the 8th bit has been clocked out. Halting the

conversion after the last needed bit is outputted is called short cycling.

Short cycling can be used to lower the power consumption in those applications that do not need a full 12-bit

resolution, or where an analog signal is being monitored until some condition occurs. For example, it may not be

necessary to use the full 12-bit resolution of the ADC121S705 as long as the signal being monitored is within

certain limits. In some circumstances, the conversion could be terminated after the first few bits. This will lower

power consumption in the converter since the ADC121S705 spends more time in power down mode and less

time in the conversion mode.

Burst Mode Operation

Normal operation of the ADC121S705 requires the SCLK frequency to be sixteen times the sample rate and the

CS rate to be the same as the sample rate. However, in order to minimize power consumption in applications

requiring sample rates below 500 kSPS, the ADC121S705 should be run with an SCLK frequency of 16 MHz and

a CS rate as slow as the system requires. When this is accomplished, the ADC121S705 is operating in burst

mode. The ADC121S705 enters into power down mode at the end of each conversion, minimizing power

consumption. This causes the converter to spend the longest possible time in power down mode. Since power

consumption scales directly with conversion rate, minimizing power consumption requires determining the lowest

conversion rate that will satisfy the requirements of the system.

TIMING CONSIDERATIONS

Proper operation requires that the fall of CS not occur simultaneously with a rising edge of SCLK. If the fall of CS

occurs during the rising edge of SCLK, the data might be clocked out one bit early. Whether or not the data is

clocked out early depends upon how close the CS transition is to the SCLK transition, the device temperature,

and characteristics of the individual device. To ensure that the data is always clocked out at a given time (the 5th

falling edge of SCLK), it is essential that the fall of CS always meet the timing requirement specified in the

Timing Specifications.

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