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ADC121S705 Datasheet(PDF) 6 Page - Texas Instruments |
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ADC121S705 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 31 page ![]() DOUT CS VIH tDIS 90% 10% 90% 10% DOUT 90% 10% VIL 3.5V 1.0V DOUT SCLK tDH tDA tCSH SCLK CS tCSSU 1 2 1.6V TO OUTPUT PIN CL 25 pF IOH IOL 2 mA 2 mA DOUT tf tr 3.5V 1.0V DOUT SCLK CS tCONV MSB tACQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HI-Z DB10 DB9 DB8 DB7 DB6 DB11 DB5 DB4 DB3 DB2 DB1 DB0 LSB tPD tCONV tACQ 3 4 5 6 1 2 7 8 MSB DB10 DB9 DB8 DB11 DOUT SCLK CS tCONV MSB tACQ tCL tCH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HI-Z HI-Z tEN DB10 DB9 DB8 DB7 DB6 DB11 DB5 DB4 DB3 DB2 DB1 DB0 tDIS LSB tPWRDWN ADC121S705 SNAS355B – DECEMBER 2006 – REVISED MARCH 2013 www.ti.com Timing Diagrams Figure 1. ADC121S705 Single Conversion Timing Diagram Figure 2. ADC121S705 Continuous Conversion Timing Diagram Figure 3. Timing Test Circuit Figure 4. Rise and Fall Times Figure 5. Hold and Access Times Figure 6. Valid CS Assertion Times Figure 7. Voltage Waveform for tDIS 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: ADC121S705 |
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