f

40MHz

CLK

(

)

1.1

f

40MHz

CLK

(

)

1.15

f

40MHz

CLK

(

)

1.23

f

40MHz

CLK

(

)

38.6

f

40MHz

CLK

(

)

1.4

(

)

40MHz

f

CLK

10.4

(

)

40MHz

f

CLK

20.4

ADS1602

SBAS341E

– DECEMBER 2004 – REVISED OCTOBER 2011

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = –40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, external VREF = +3V, VCM =

+1.45V, and RBIAS = 37kΩ, unless otherwise noted.

ADS1602

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital Filter Characteristics

Passband

0

MHz

Passband ripple

±0.001

dB

–0.1dB attenuation

MHz

Passband transition

–3dB attentuation

MHz

Stop band

MHz

Stop band attenuation

75

dB

Group delay

μs

Settling time

Complete settling

μs

Static Specifications

Resolution

16

Bits

No missing codes

16

Bits

Input-referred noise

0.5

0.85

LSB, rms

Integral nonlinearity

–1dBFS signal

0.75

LSB

Differential nonlinearity

0.25

LSB

Offset error

–0.1

%FSR

Offset error drift

–0.1

ppmFSR/

°C

Gain error

0.25(1)

%

Gain error drift

Excluding reference drift

10

ppm/

°C

Common-mode rejection

At dc

75

dB

Power-supply rejection

At dc

65

dB

Internal Voltage Reference

REFEN = low

VREF = (VREFP – VREFN)

2.75

3

3.25

V

VREFP

3.5

4

4.3

V

VREFN

0.5

1

1.3

V

VMID

2.3

2.5

2.7

V

VREF drift

50

ppm/

°C

Startup time

15

ms

External Voltage Reference

REFEN = high

VREF = (VREFP – VREFN)

2

3

3.25

V

VREFP

3.5

4

4.25

V

VREFN

0.5

1

1.5

V

VMID

2.3

2.5

2.6

V

(1)

There is a constant gain error of 2.5% in addition to the variable gain error of

±0.25%. Therefore, the gain error is 2.5 ± 0.25%.

4

Copyright

© 2004–2011, Texas Instruments Incorporated