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ADS1602IPFBT Datasheet(PDF) 7 Page - Texas Instruments |
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ADS1602IPFBT Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 30 page  36 35 34 33 32 31 30 29 28 27 26 25 DGND NC DVDD DGND FSO FSO DOUT DOUT SCLK SCLK NC NC 1 2 3 4 5 6 7 8 9 10 11 12 AGND AVDD AGND AINN AINP AGND AVDD RBIAS AGND AVDD AGND AVDD 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 37 24 ADS1602 TQFPPACKAGE (TOPVIEW) ADS1602 www.ti.com SBAS341E – DECEMBER 2004 – REVISED OCTOBER 2011 PIN ASSIGNMENTS TERMINAL FUNCTIONS TERMINAL FUNCTION DESCRIPTION NAME NO. AGND 1, 3, 6, 9, 11, 39, 41 Analog Analog ground AVDD 2, 7, 10, 12, 42 Analog Analog supply AINN 4 Analog input Negative analog input AINP 5 Analog input Positive analog input RBIAS 8 Analog Terminal for external analog bias setting resistor. REFEN 13 Digital input: active low Internal reference enable. Internal pull-down resistor of 170k Ω to DGND. NC 14, 16, 24 –26, 35 Do not connect These terminals must be left unconnected. RPULLUP 15 Digital input Pull-up to DVDD with 10k Ω resistor (see Figure 53). PD 17 Digital input: active low Power-down all circuitry. Internal pull-up resistor of 170k Ω to DGND. DVDD 18, 23, 34 Digital Digital supply DGND 19, 22, 33, 36, 38 Digital Digital ground SYNC 20 Digital input Synchronization control input OTR 21 Digital output Indicates analog input signal is out of range. SCLK 28 Digital output Serial clock output SCLK 27 Digital output Serial clock output, complementary signal. DOUT 30 Digital output Data output DOUT 29 Digital output Data output, complementary signal. FSO 32 Digital output Frame synchronization output FSO 31 Digital output Frame synchronization output, complementary signal. IOVDD 37 Digital Digital I/O supply CLK 40 Digital input Clock input VCAP 43 Analog Terminal for external bypass capacitor connection to internal bias voltage. VREFN 44, 45 Analog Negative reference voltage VMID 46 Analog Midpoint voltage VREFP 47, 48 Analog Positive reference voltage Copyright © 2004–2011, Texas Instruments Incorporated 7 |
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