1.0

0.8

0.6

0.4

0.2

0

−0.2

−0.4

−0.6

−0.8

−1.0

0

512

1024

1536

2048

2560

3072

3584

4096

Code

f

IN = 5MHz

90

80

70

60

50

40

30

20

10

0

−70

−60

−50

−40

−30

−20

−10

0

Input Amplitude (dBFS)

f

IN = 5MHz

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

90

80

70

60

50

40

30

20

10

0

−70

−60

−50

−40

−30

−20

−10

0

Input Amplitude (dBFS)

f

IN = 10MHz

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

95

90

85

80

75

70

65

60

20

30

40

50

60

70

80

Duty Cycle (%)

f

IN = 5MHz

SNR

SFDR

SINAD

95

90

85

80

75

70

65

60

0

5

10

15

20

25

30

35

40

45

50

Input Frequency (MHz)

SFDR

SNR

95

90

85

80

75

70

65

60

55

50

15

20

25

30

35

40

45

50

55

60

Sample Rate (MSPS)

SFDR

f

IN = 5MHz

SNR

SINAD

ADS5271

www.ti.com...................................................................................................................................................... SBAS313C – JUNE 2004 – REVISED JANUARY 2009

TYPICAL CHARACTERISTICS (continued)

Typical values are at TA = +25C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,

–1dBFS, ISET = 56.2kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.

INTEGRAL NONLINEARITY

SWEPT INPUT POWER

Figure 7.

Figure 8.

SWEPT INPUT POWER

DYNAMIC PERFORMANCE vs DUTY CYCLE

Figure 9.

Figure 10.

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

DYNAMIC PERFORMANCE vs SAMPLE RATE

Figure 11.

Figure 12.

Copyright © 2004–2009, Texas Instruments Incorporated

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