RESET

LAYOUT OF PCB WITH PowerPAD

POWER-DOWN MODE

CONNECTING HIGH-SPEED,

ADS5271

www.ti.com...................................................................................................................................................... SBAS313C – JUNE 2004 – REVISED JANUARY 2009

are kept to the minimum possible values. Use of

ground planes in the board as well as large

After the supplies have stabilized, it is necessary to

decoupling

capacitors

between

the

supply

and

give the device an active RESET pulse. This results

ground lines are necessary to get the best possible

in all internal registers resetting to their default value

SNR from the device.

of 0 (inactive). Without a reset, it is possible that

It is recommended that the isolation be maintained on

some registers may be in their non-default state on

board by using separate supplies to drive AVDD and

power-up. This may cause the device to malfunction.

LVDD, as well as separate ground planes for AVSS

When a reset is active, the device outputs ‘0’ code on

and LVSS.

all channels. However, the LVDS output clocks are

unaffected by reset.

The use of LVDS buffers reduces the injected noise

considerably,

compared

to

CMOS

buffers.

The

current in the LVDS buffer is independent of the

THERMALLY-ENHANCED PACKAGES

direction of switching. Also, the low output swing as

well as the differential nature of the LVDS buffer

The ADS5271 is housed in an 80-lead PowerPAD

results in low-noise coupling.

thermally-enhanced package. To make optimum use

of

the

thermal

efficiencies

designed

into

the

PowerPAD package, the printed circuit board (PCB)

must be designed with this technology in mind.

The ADS5271 has a power-down pin, referred to as

Please refer to SLMA004 PowerPAD brief PowerPAD

PD. Pulling PD high causes the device to enter the

Made Easy (refer to our web site at www.ti.com),

power-down mode. In this mode, the reference and

which addresses the specific considerations required

clock circuitry, as well as all the channels, are

when integrating a PowerPAD package into a PCB

powered down. Device power consumption drops to

design. For more detailed information, including

less than 100mW in this mode. In power-down mode,

thermal modeling and repair procedures, please see

the internal buffers driving REFT and REFB are

the

technical

brief

SLMA002,

PowerPAD

tri-stated and their outputs are forced to a voltage

Thermally-Enhanced Package (www.ti.com).

roughly equal to half of the voltage on AVDD. Speed

of recovery from power-down mode depends on the

Interfacing High-Speed LVDS Outputs (SBOA104),

value of the external capacitance on the REFT and

an application report discussing the design of a

REFB pins. For capacitances on REFT and REFB less

simple deserializer that can deserialize LVDS outputs

than 1

µF, the reference voltages settle to within 1%

up to 840Mbps, can also be found on the TI web site

of their steady-state values in less than 500

µs.

(www.ti.com).

Individual channels can also be selectively powered

down by programming registers.

MULTI-CHANNEL ADCs TO XILINX FPGAs

The ADS5271 also has an internal circuit that

monitors the state of stopped clocks. If ADCLK is

A separate application note (XAPP774) describing

stopped for longer than 300ns (or if it runs at a speed

how to connect TI's high-speed, multi-channel ADCs

less than 3MHz), this monitoring circuit generates a

with serial LVDS outputs to Xilinx FPGAs can be

logic signal

that

puts

the

device

in

a

partial

downloaded

directly

from

the

Xilinx

web

site

power-down

state.

As

a

result,

the

power

(http://www.xilinx.com).

consumption of the device is reduced when ADCLK is

stopped.

The

recovery

from

such

a

partial

power-down takes ap- proximately 100

µs; this is

described in Table 2.

Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage

DESCRIPTION

TYP

REMARKS

Recovery from power-down mode (PD = 1 to PD = 0).

500

µs

Capacitors on REFT and REFB less than 1µF.

Recovery from momentary clock stoppage ( < 300ns).

10

µs

Recovery from extended clock stoppage ( > 300ns).

100

µs

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