ADS5424IPGPR datasheet(19/29 Pages) TI2

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ADS5424

SLWS157B − JANUARY 2005 − REVISED JANUARY 2010

www.ti.com

APPLICATION INFORMATION

2.7 pF

14-Bit

105 MSPS

AIN

AIN VREF

ADS5424

+5V

THS 4509

348

Ω

348

Ω

100

Ω

100

Ω

69.8

Ω

VIN

From

Ω

Source

225

Ω

225

Ω

69.8

Ω

49.9

Ω

49.9

Ω

0.22

µF

0.22

µF

0.1

µF

0.1

µF

0.22

µF

Figure 41. Using the THS4509 With the ADS5424

fIN − Input Frequency − MHz

PERFORMANCE

INPUT FREQUENCY

SNR (dBFS)

SFDR (dBc)

Figure 42. Performance vs Input Frequency for

the THS4509 + ADS5424 Configuration

CLK

ADS5424

CLK

Square Wave or

Sine Wave

0.01

µF

0.01

µF

Figure 43. Single-Ended Clock

CLOCK INPUTS

The ADS5424 clock input can be driven with either a

differential clock signal or a single-ended clock input,

with little or no difference in performance between both

configurations. In low input frequency applications,

where jitter may not be a big concern, the use of

single-ended clock (see Figure 43) could save some

cost and board space without any trade-off in

performance. When driven on this configuration, it is

best to connect CLKM (pin 11) to ground with a 0.01

µF

capacitor, while CLKP is ac-coupled with a 0.01

µF

capacitor to the clock source, as shown in Figure 40.

CLK

ADS5424

CLK

0.1

µF

1:4

Clock

Source

MA3X71600LCT−ND

Figure 44. Differential Clock

Nevertheless, for jitter sensitive applications, the use of

a differential clock will have some advantages (as with

any other ADCs) at the system level. The first

advantage is that it allows for common-mode noise

rejection at the PCB level. A further analysis (see

Clocking High Speed Data Converters, SLYT075)

reveals one more advantage. The following formula

describes the different contributions to clock jitter:

(Jittertotal)2 = (EXT_jitter)2+ (ADC_jitter)2=

(EXT_jitter)2 + (ADC_int)2 + (K/clock_slope)2

The first term would represent the external jitter, coming

from the clock source, plus noise added by the system

on the clock distribution, up to the ADC. The second

term is the ADC contribution, which can be divided in

two portions. The first does not depend directly on any

external factor. That is the best we can get out of our

ADC. The second contribution is a term inversely

proportional to the clock slope. The faster the slope, the

smaller this term will be. As an example, we could

compute the ADC jitter contribution from a sinusoidal

input clock of 3 Vpp amplitude and Fs = 80 MSPS:

ADC_jitter = sqrt ((150fs)2+ (5 x 10−5/(1.5 x 2 x PI x 80

x 106))2) = 164fs

The use of differential clock allows for the use of bigger

clock amplitudes without exceeding the absolute

maximum ratings. This, on the case of sinusoidal clock,

results on higher slew rates which minimizes the impact

of the jitter factor inversely proportional to the clock

slope.

ADS5424IPGPR Datasheet(PDF) 19 Page - Texas Instruments

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