ADS5424IPGPR datasheet(6/29 Pages) TI2

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ADS5424

SLWS157B − JANUARY 2005 − REVISED JANUARY 2010

www.ti.com

TIMING CHARACTERISTICS(3)

Over full temperature range, AVDD = 5 V, DRVDD = 3.3 V, sampling rate = 105 MSPS

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

Aperture Time

Aperture delay

500

Clock slope independent aperture uncertainity (jitter)

150

Clock slope dependent jitter factor

µV

Clock Input

tCLK

Clock period

9.5

tCLKH(1)

Clock pulsewidth high

4.75

tCLKL(1)

Clock pulsewidth low

4.75

Clock to DataReady (DRY)

tDR

Clock rising 50% to DRY falling 50%

2.8

3.9

4.7

tC_DR

Clock rising 50% to DRY rising 50%

tDR +

tCLKH

tC_DR_50%

Clock rising 50% to DRY rising 50% with 50% duty cycle clock

7.6

8.7

9.5

Clock to DATA, OVR(4)

Data VOL to data VOH (rise time)

Data VOH to data VOL (fall time)

Latency

Cycles

tsu(C)

Valid DATA(2) to clock 50% with 50% duty cycle clock (setup time)

1.8

3.4

tH(C)

Clock 50% to invalid DATA(2) (hold time)

2.6

3.6

DataReady (DRY) to DATA, OVR(4)

tsu(DR)_50%

Valid DATA(2) to DRY 50% with 50% duty cycle clock (setup time)

1.8

2.6

th(DR)_50%

DRY 50% to invalid DATA(2) with 50% duty cycle clock (hold time)

3.9

4.4

(1) See Figure 21 for more information.

(2) See VOH and VOL levels.

(3) All values obtained from design and characterization.

(4) Data is updated with clock rising edge or DRY falling edge.

N+1

N+2

N+3

N+4

N−1

N−2

N−3

tsu(C)

th(C)

th(DR)

N + 1

N + 2

N + 3

N + 4

tC_DR

tCLK

tCLKL

CLK, CLK

D[13:0], OVR

DRY

AIN

tCLKH

tDR

tsu(DR)

Figure 1. Timing Diagram

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