ADS5424IPGPR datasheet(7/29 Pages) TI2

7 / 29 page

ADS5424

SLWS157B − JANUARY 2005 − REVISED JANUARY 2010

www.ti.com

PIN CONFIGURATION

15 16

D0 (LSB)

DMID

GND

DRVDD

OVR

DNC

AVDD

GND

AVDD

GND

DRVDD

GND

VREF

GND

CLK

GND

AVDD

GND

AIN

GND

18 19 20 21

PJY PACKAGE

(TOP VIEW)

51 50 49 48 47

44 43 42

22 23 24 25 26

41 40

GND

PIN ASSIGNMENTS

TERMINAL

NAME

NO.

DESCRIPTION

DRVDD

1, 33, 43

3.3 V power supply, digital output stage only

GND

2, 4, 7, 10, 13, 15,

17, 19, 21, 23, 25,

27, 29, 34, 42

Ground

VREF

2.4 V reference. Bypass to ground with a 0.1-

µF microwave chip capacitor.

CLK

Clock input. Conversion initiated on rising edge.

CLK

Complement of CLK, differential input

AVDD

8, 9, 14, 16, 18,

22, 26, 28, 30

5 V analog power supply

AIN

Analog input

AIN

Complement of AIN, differential analog input

Internal voltage reference. Bypass to ground with a 0.1-

µF chip capacitor.

Internal voltage reference. Bypass to ground with a 0.1-

µF chip capacitor.

DNC

Do not connect

OVR

Overrange bit. A logic level high indicates the analog input exceeds full scale.

DMID

Output data voltage midpoint. Approximately equal to (DVCC)/2

D0 (LSB)

Digital output bit (least significant bit); two’s complement

D1−D5, D6−D12

37−41, 44−50

Digital output bits in two’s complement

D13 (MSB)

Digital output bit (most significant bit); two’s complement

DRY

Data ready output

ADS5424IPGPR Datasheet(PDF) 7 Page - Texas Instruments

ADS5424IPGPR Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Download

Link URL