I

(t)=

PEAK

VINAC(t)

T

´

ON

L

I

(t)=

AVG

VINAC(t)

T

´

ON

2

L

´

T

=K (V

125mV)

-

ON

T

COMP

T

=K

4.825V

´

ON(max)

T

UCC28061-Q1

SLUSB01 – MARCH 2012

www.ti.com

APPLICATION INFORMATION

Theory of Operation

The UCC28061-Q1 contains the control circuits for two boost pulse-width modulation (PWM) power converters.

The boost PWM power converters ramp current in the boost inductors for a time period proportional to the

voltage on the error amplifier output. Each power converter then turns off the power MOSFET until current in the

boost inductor decays to 0, as sensed on the zero current detection inputs (ZCDA and ZCDB). Once the inductor

current decays to 0, the power converter starts another cycle. This on/off cycling produces a triangle wave of

current, with peak current set by the on-time and power mains input voltage, as shown in Equation 1.

(1)

The average line current is exactly equal to half of the peak line current, as shown in Equation 2.

(2)

With TON and L being essentially constant during an ac line period, the resulting triangular current waveform

during each switching cycle has an average value proportional to the instantaneous value of the rectified ac line

voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a near-

unity power factor.

The outputs of the two PWMs operate 180° out-of-phase so that power-line ripple current for the two PWMs is

greatly reduced from the ripple current of each individual PWM. This design reduces ripple current at the input

and output, allowing the reduction in size and cost of input and output filters.

Optimal phase balance occurs if the individual power stages and the on-times are well-matched. Mismatches in

inductor values do not affect the phase relationship.

On-Time Control, Maximum Frequency Limiting, and Restart Timer

Gate drive on-time varies with the error amplifier output voltage by a factor called KT, as shown in Equation 3.

(3)

Where:

VCOMP is the output of the error amplifier, and 125 mV is a modulator offset.

To provide smooth transition between two-phase and single-phase operation, KT increases by a factor of two in

single-phase mode:

•

KTLS = 2 × KTL; active in single-phase operation

The clamped maximum output of the error amplifier is limited to 4.95 V. This value, less the 125 mV modulator

offset, limits on-time to Equation 4.

(4)

This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage level.

The switching frequency of each phase is limited by minimum period timers. If the current decays to 0 before the

minimum period timer elapses, turn-on is delayed, resulting in discontinuous phase current.

The restart timer ensures starting under all circumstances by restarting both phases if either phase ZCD input

has not transitioned high-to-low for approximately 200

μs. To prevent the circuit from operating in continuous

conduction mode (CCM), the restart time does not trigger turn-on until both phase currents return to 0.

16

Submit Documentation Feedback

Copyright © 2012, Texas Instruments Incorporated

Product Folder Link(s): UCC28061-Q1