UCC28061-Q1

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SLUSB01 – MARCH 2012

Open-Loop Protection

If the feedback loop is disconnected from the device, a current source internal to the UCC28061-Q1 pulls the

VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device is disabled. When disabled,

supply current decreases, and both gate drive outputs and COMP are actively pulled low. The device is re-

enabled when VSENSE rises above 1.25 V. At that time, the gate drive outputs begin switching under PWM

control.

The device can be externally disabled by grounding the VSENSE pin with an open-drain or open-collector driver.

When disabled, device supply current drops and COMP is actively pulled low. When VSENSE is released, the

device soft-starts. This disable method forces the device into standby mode and minimizes its power

consumption. This feature is particularly useful when standby power is a key design aspect.

If the feedback loop is disconnected from ground, the VSENSE voltage goes high. When VSENSE rises above

the over-voltage protection threshold, both gate drive outputs go low, and COMP is actively pulled low. The

device is re-enabled when VSENSE falls back into range. At that time, the gate drive outputs begin switching

under PWM control. The VSENSE pin is internally clamped to protect the device from damage under this

condition.

Soft-Start

The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to

AGND charges from a low level to the final value. This process implements a soft-start, with a time constant set

by the output current of the error amplifier and the value of the compensation capacitors. In the event of a

brownout, logic disable, or VCC undervoltage fault, COMP is actively pulled low so the PWM soft-starts after this

event is cleared. The UCC28061-Q1 also asserts soft start when output over-voltage is detected. Even if a fault

event happens very briefly, soft-start fully discharges the compensation components before resuming operation,

ensuring soft-starting. See Figure 27 for details.

Light-Load Operation

As load current decreases, the error amplifier commands less input current by lowering the COMP voltage. If

PHB (normally connected to COMP) falls below 0.8 V at low input line (or 1.1 V at high input line), channel B

stops switching and channel A on-time doubles to compensate. If COMP falls below 150 mV, channel A also

stops switching and the loop enters a hysteretic control mode. The PWM skips cycles to maintain regulation.

Instead of skipping cycles, the UCC28061-Q1 allows on-time reduction smoothly to zero as load decreases.

However, maximum switching frequency is limited, so at very light load, discountinuous operation is possible.

Command for the Downstream Converter

In the UCC28061-Q1, the PWMCNTL pin is used to coordinate the PFC stage with a downstream converter.

Through the HVSEN pin, the output voltage is sensed. When the output voltage is within the desired range, the

PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. The enable

threshold and hysteresis can be adjusted independently through the voltage divider ratio and resistor values. The

HVSEN pin is also used for the FailSafe over-voltage protection. When designing the voltage divider, make sure

this FailSafe over-voltage protection level is set above normal operating levels.

VCC Undervoltage Protection

VCC must rise above the undervoltage threshold for the PWM to begin functioning. If VCC drops below the

threshold during operation, both gate drive outputs and COMP are actively pulled low. VCC must rise above the

threshold for PWM function to restart.

VCC

VCC is connected to a bias supply of between 13 V and 21 V. When powered from a poorly-regulated supply, an

external zener diode is recommended to prevent excessive current into VCC.

Copyright © 2012, Texas Instruments Incorporated

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