TMS28F200AST datasheet(15/79 Pages) TI

15 / 79 page

TMS28F002Axy, TMS28F200Axy

262144 BY 8-BIT/131072 BY 16-BIT

AUTO-SELECT BOOT-BLOCK FLASH MEMORIES

SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

erase operations (continued)

Erase-setup and erase-confirm commands are latched on the rising edge of E or W, whichever occurs first.

Block addresses are latched during the block-erase-confirm command on the rising edge of E or W (see

Figure 14 and Figure 15). When the block-erase-confirm command is complete, the WSM automatically

executes a sequence of events to complete the block erasure. During this sequence, the block is

programmed with logic 0s, data is verified, all bits in the block are erased, and finally, verification is

performed to ensure that all bits are erased correctly. Monitoring of the erase operation is possible through

the status register (see the “read status register” paragraph in the “read operations” subsection).

D erase-suspend/erase-resume

During the execution of an erase operation, the erase-suspend command (B0h ) can be entered to direct the

WSM to suspend the erase operation. Once the WSM has reached the suspend state, it allows the CSM to

respond only to the read-array, read-status-register, and erase-resume commands. During the

erase-suspend operation, array data should be read from a block other than the one being erased. To

resume the erase operation, an erase-resume command (D0h ) must be issued to cause the CSM to clear

the suspend state previously set (see Figure 5 and Figure 6).

automatic power-saving mode

Substantial power savings are realized during periods when the array is not being read and the device is in the

active mode. During this time, the device switches to the automatic power-saving (APS) mode. When the device

switches to this mode, ICC is typically reduced from 40 mA to 1 mA (IOUT = 0 mA). The low level of power is

maintained until another read operation is initiated. In this mode, the I/O pins retain the data from the last

memory address read until a new address is read. This mode is entered automatically if no address or control

pins toggle within approximately a 200-ns time-out period. At least one transition on E must occur after power

up to activate this mode.

reset / deep power-down mode

Very low levels of power consumption can be attained by using a special pin, RP, to disable internal device

circuitry. When RP is at a CMOS logic-low level of 0.0 V

± 0.2 V, a much lower ICC value or power is achievable.

This is important in portable applications where extended battery life is of major concern.

A recovery time is required when exiting from deep power-down mode. For a read-array operation, a

minimum of td(RP) is required before data is valid, and a minimum of trec(RPHE) and trec(RPHW) in deep

power-down mode is required before data input to the CSM can be recognized. With RP at ground, the WSM

is reset and the status register is cleared, effectively eliminating accidental programming to the array during

system reset. After restoration of power, the device does not recognize any operation command until RP is

returned to a VIH or VHH level.

Should RP go low during a program or erase operation, the device powers down and, therefore, becomes

nonfunctional. Data being written or erased at that time becomes invalid or indeterminate, requiring that the

operation be performed again after power restoration.

power supply detection

RP must be connected to the system reset / power down signal to ensure that proper synchronization is

maintained between the CPU and the flash memory operating modes. The default state after power up and exit

from deep power-down mode is read array. RP also is used to indicate that the power supply is stable so that

the operating supply voltage can be established (3 V, 3.3 V, or 5 V). Figure 10 shows the proper power-up

sequence. To reset the operating supply voltage, the device must be completely powered off (VCC = 0 V) before

the new supply voltage is detected.

TMS28F200AST Datasheet(PDF) 15 Page - Texas Instruments

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