SM320VC33 datasheet(32/53 Pages) TI2

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CVDD

0 --100 Ω

0.1 F

0.01

0 --100 Ω

VSS

PLLVDD

PLLVSS

XOUT

XIN

Crystal

EXTCLK

PLLVSS

CVDD

100 Ω

PLLVDD

0.1 F

0.01 F

SM320VC33, SMJ320VC33

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

www.ti.com

Table 3. Typical Crystal Circuit Loading

FREQUENCY (MHz)

Rd (Ω)

C1 (pF)

C2 (pF)

CL(1) (pF)

RL(1) (

Ω)

4.7k

200

2.2k

470

(1)

CL and RL are typical internal series load capacitance and resistance of the crystal.

Figure 26. Self-Oscillation Mode

8.2.4 PLL Isolation

The internal PLL supplies can be directly connected to CVDD and VSS (0-

Ω case), partially isolated as shown in

Figure 26, or fully isolated as shown in Figure 27. The RC network prevents the PLL supplies from turning high-

frequency noise in the CVDD and VSS supplies into jitter.

Figure 27. PLL Isolation Circuit Diagram

8.2.5 Clock and PLL Considerations on Initialization

On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER, or IDLE2, or the PLL could be in

an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which

the device will synchronously terminate any external activity.

The 5× Fclkin PLL of the 320VC33 contains an 8-bit PLL–LOCK counter that causes the PLL to output a

frequency of Fclkin / 2 during the initial ramp. However, this counter does not increment while RESET is low or in

the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of reset for

the PLL to output to clear this counter. The following describes the setup and behavior that is observed. Power is

applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still low) and

the PLL appears to lock onto the input clock, producing the expected ×5 output frequency. RESET is driven high

and the PLL output immediately drops to Fclkin / 2 for up to 256 input cycles or 128 of the Fclkin / 2 output

cycles. The PLL/CPU clock then switches to ×5 mode.

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