SM320VC33 datasheet(13/53 Pages) TI2

13 / 53 page

SM320VC33, SMJ320VC33

www.ti.com

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

6.14 Timing Requirements for HOLD/HOLDA

see Figure 17 and Figure 18

MIN

MAX

UNIT

tsu(HOLD-H1L)

Setup time, HOLD before H1 low

tw(HOLD)

Pulse duration, HOLD low

3tc(H)

(1)

Not production tested.

6.15 Timing Requirements for Peripheral Pin General-Purpose I/O

see Figure 19 and Figure 20

(1)

MIN

MAX

UNIT

tsu(GPIO-H1L)

Setup time, general-purpose input before H1 low

3(2)

th(H1L-GPIO)

Hold time, general-purpose input after H1 low

0(2)

(1)

Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents of

internal-control registers associated with each peripheral.

(2)

Not production tested

6.16 Timing Requirements for Timer Pin

see Figure 21 and Figure 22

(1)

MIN

MAX

UNIT

tsu(TCLK-H1L)

(2)

Setup time, TCLK external before H1 low

3(3)

th(H1L-TCLK)

(2)

Hold time, TCLK external after H1 low

(1)

Valid logic-level periods and polarity are specified by the contents of the internal control registers.

(2)

These requirements are applicable for a synchronous input clock.

(3)

Not production tested

6.17 Timing Requirements for IEEE-1149.1 Test Access Port

see Figure 24

MIN

MAX

UNIT

tsu(TMS-TCKH)

Setup time, TMS/TDI to TCK high

5(1)

th(TCKH-TMS)

Hold time, TMS/TDI from TCK high

5(1)

td(TCKL-TDOV)

Delay time, TCK low to TDO valid

0(1)

10(1)

tr (TCK)

Rise time, TCK

3(1)

tf (TCK)

Fall time, TCK

3(1)

(1)

Not production tested

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