SM320VC33 datasheet(5/53 Pages) TI2

5 / 53 page

SM320VC33, SMJ320VC33

www.ti.com

SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

Pin Functions

CONDITIONS WHEN

TYPE(1)

DESCRIPTION

SIGNAL IS Z TYPE(2)

NAME

QTY

PRIMARY-BUS INTERFACE

D31- D0

I/O/Z

32-bit data port

Data port bus keepers. (See Figure 30)

A23- A0

O/Z

24-bit address port

R/W

O/Z

Read/write. R/W is high when a read is performed and low when a write is

performed over the parallel interface.

STRB

O/Z

Strobe. For all external-accesses

PAGE0 to

O/Z

Page strobes. Four decoded page strobes for external access

PAGE3

RDY

Ready. RDY indicates that the external device is prepared for a transaction

completion.

HOLD

Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 to

A0, D31 to D0, STRB, and R/W are placed in the high-impedance state and all

transactions over the primary-bus interface are held until HOLD becomes a logic

high or until the NOHOLD bit of the primary-bus-control register is set.

HOLDA

O/Z

Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD.

HOLDA indicates that A23 to A0, D31 to D0, STRB, and R/W are in the high-

impedance state and that all transactions over the bus are held. HOLDA is high in

response to a logic-high of HOLD or the NOHOLD bit of the primary-bus-control

CONTROL SIGNALS

RESET

Reset. When RESET is a logic low, the device is in the reset condition. When

RESET becomes a logic high, execution begins from the location specified by the

reset vector.

EDGEMO

Edge mode. Enables interrupt edge mode detection.

INT3 to

External interrupts

INT0

IACK

O/Z

Internal acknowledge. IACK is generated by the IACK instruction. IACK can be

used to indicate when a section of code is being executed.

MCBL/MP

Microcomputer bootloader/microprocessor mode-select

SHZ

Shutdown high impedance. When active, SHZ places all pins in the high-

impedance state. SHZ can be used for board-level testing or to ensure that no

dual-drive conditions occur.

CAUTION: A low on SHZ corrupts the device memory and register contents.

Reset the device with SHZ high to restore it to a known operating condition.

XF1, XF0

I/O/Z

External flags. XF1 and XF0 are used as general-purpose I/Os or to support

interlocked processor instruction.

SERIAL PORT 0 SIGNALS

CLKR0

I/O/Z

Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0

receiver.

CLKX0

I/O/Z

Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0

transmitter.

DR0

I/O/Z

Data-receive. Serial port 0 receives serial data on DR0.

DX0

I/O/Z

Data-transmit output. Serial port 0 transmits serial data on DX0.

FSR0

I/O/Z

Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-

receive process using DR0.

FSX0

I/O/Z

Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-

transmit process using DX0.

TIMER SIGNALS

TCLK0

I/O/Z

Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As

an output, TCLK0 outputs pulses generated by timer 0.

(1)

I = input, O = output, Z = high-impedance state

(2)

S = SHZ active, H = HOLD active, R = RESET active

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