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SM320VC33 Datasheet(PDF) 1 Page - Texas Instruments |
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SM320VC33 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 53 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SM320VC33, SMJ320VC33 SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015 SMx320VC33 Digital Signal Processor 1 Features • Conditional Calls and Returns • Interlocked Instructions for Multiprocessing 1 • High-Performance Floating-Point Digital Signal Support Processor (DSP) • Bus-Control Registers Configure Strobe-Control – SMx320VC33-150 Wait-State Generation – 13-ns Instruction Cycle Time • 1.8-V (Core) and 3.3-V (I/O) Supply Voltages – 150 Million Floating-Point Operations per Second (MFLOPS) 2 Description – 75 Million Instructions per Second (MIPS) The SMx320VC33 DSP is a 32-bit, floating-point • 34K × 32-Bit (1.1-Mbit) On-Chip Words of Dual- processor manufactured in 0.18- μm four-level-metal Access Static Random-Access Memory (SRAM) CMOS (TImeline) technology. The SMx320VC33 is Configured in 2 × 16K plus 2 × 1K Blocks to part of the SM320C3x™ generation of DSPs from Texas Instruments. Improve Internal Performance • x5 Phase-Locked Loop (PLL) Clock Generator The SM320C3x internal busing and special digital- signal-processing instruction set have the speed and • Very-Low Power: <200 mW at 150 MFLOPS flexibility to execute up to 150 MFLOPS. The • 32-Bit High-Performance CPU SMx320VC33 optimizes speed by implementing • 16-/32-Bit Integer and 32-/40-Bit Floating-Point functions in hardware that other processors Operations implement through software or microcode. This hardware-intensive approach provides performance • Four Internally Decoded Page Strobes to Simplify previously unavailable on a single chip. Interface to I/O and Memory Devices • Boot-Program Loader The SMx320VC33 can perform parallel multiply and ALU operations on integer or floating-point data in a • EDGEMODE Selectable External Interrupts single cycle. Each processor also possesses a • 32-Bit Instruction Word, 24-Bit Addresses general-purpose register file, a program cache, • Eight Extended-Precision Registers dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a • Fabricated Using the 0.18- μm (leff – Effective Gate short machine-cycle time. These features result in Length) TImeline™ Technology by Texas high performance and ease of use. General-purpose Instruments applications are greatly enhanced by the large • On-Chip Scan-Based Emulation Logic, IEEE Std address space, multiprocessor interface, internally 1149.1 (JTAG) and externally generated wait states, one external • On-Chip Memory-Mapped Peripherals: interface port, two timers, one serial port, and multiple-interrupt structure. – One Serial Port – Two 32-Bit Timers The SM320C3x supports a wide variety of system applications from host processor to dedicated – Direct Memory Access (DMA) Coprocessor for coprocessor. High-level-language support is easily Concurrent I/O and CPU Operation implemented through a register-based architecture, • 164-Pin Low-Profile Quad Flatpack (HFG Suffix) large address space, powerful addressing modes, • 144-Pin Non-Hermetic Ceramic Ball Grid Array flexible instruction set, and well-supported floating- point arithmetic. (CBGA) (GNM Suffix) • Two Address Generators With Eight Auxiliary Device Information(1) Registers and Two Auxiliary Register Arithmetic PART NUMBER PACKAGE BODY SIZE (NOM) Units (ARAUs) SM320VC33 CFP (164) 12.00 mm × 12.00 mm • Two Low-Power Modes SMJ320VC33 CFP (164) 29.09 mm × 29.09 mm • Two- and Three-Operand Instructions (1) For all available packages, see the orderable addendum at • Parallel Arithmetic/Logic Unit (ALU) and Multiplier the end of the data sheet. Execution in a Single Cycle • Block-Repeat Capability • Zero-Overhead Loops With Single-Cycle Branches 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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