SM320VC33 datasheet(39/53 Pages) TI2

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FSX(EXT)

FSX(INT)

FSR

CLKX/R

Bit 0

Bit n-1

Bit n-2

Bit n-1

Bit n-2

td(H1H-SCK)

t c(SCK)

tw(SCK)

tr(SCK)

t f(SCK)

t d(CLKX--DX)

t su(DR--CLKRL)

t h(CLKRL--DR)

td(CLKX--FSX)

t su(FSR--CLKRL)

td(CLKX--FSX)

t h(SCKL--FS)

tsu(FSX--CLKX)

d(CLKX--DX)V

t dis(CLKX--DXZ)

SM320VC33, SMJ320VC33

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SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015

further restricted in pulse width as defined by tw(INT) in Timing Requirements for INT3 to INT0 Response.

When EDGEMODE = 1, the falling edge of the INT0 to INT3 pins are detected using synchronous logic (see

Figure 28). The pulse low and high time should be two CPU clocks or greater.

The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has

been cleared.

If the specified timings are met, the exact sequence shown in Figure 15 occurs; otherwise, an additional delay of

one clock cycle is possible.

8.2.18 Interrupt-Acknowledge Timing

The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and

goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.

Switching Characteristics for IACK defines the timing parameters for the IACK signal.

NOTE

The IACK instruction can be executed at anytime to signal an event. It is most often used

within an interrupt routine to signal which interrupt has occurred. The IACK instruction

must be executed to generate the IACK pulse.

8.2.19 Data-Rate Timing Modes

Unless otherwise indicated, the data-rate timings shown in Figure 34 and Figure 35 are valid for all serial-port

modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s

Guide (SPRU031).

The serial-port timing parameters are defined in Timing Requirements for Serial Port.

Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.

Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

Figure 34. Fixed Data-Rate Mode Timing

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