7.5 Electrical Characteristics (continued)

VSUP = 7 V to 27 V, TA = –40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

INH PIN

Vo

DC output voltage

Transient voltage

-0.3

VSUP+0.3

V

IO

Output current

-50

2

mA

Ron

On state resistance

Between VSUP and INH, INH = 2 mA

drive, Normal or Standby Mode

25

40

100

Ω

IIKG

Leakage current

Low Power mode, 0 < INH < VSUP

-5

0

5

µA

NWake PIN

VIL

Low-level input voltage(2)

-0.3

VSUP-3.3

V

VIH

High-level input voltage(2)

VSUP-1

VSUP+0.3

V

Pull-up current

NWake = 0 V

-40

-10

-4

µA

IIKG

Leakage current

VSUP = NWake

-5

0

5

µA

THERMAL SHUTDOWN

Shutdown junction thermal

temperature

185

°C

(1)

Typical values are given for VSUP = 14 V at 25°C.

(2)

All voltages are defined with respect to ground; positive currents flow into the TPIC1021 device.

(3)

In the dominant state the supply current increases as the supply voltage increases due to the integrated LIN responder termination

resistance. At higher voltages the majority of supply current is through the termination resistance. The minimum resistance of the

LIN responder termination is 20 kΩ so the maximum supply current attributed to the termination is: ISUP (dom) max termination ≈ (VSUP –

(VLIN_Dominant+0.7 V) / 20 kΩ.

7.6 Timing Requirements

MIN

NOM

MAX UNIT

D1

Duty cycle 1(1) (2)

THREC(max) = 0.744×VSUP, THDOM(max) = 0.581×VSUP, VSUP

= 7.0 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 7-1

0.396

D2

Duty cycle 2(1) (2)

THREC(max) = 0.284×VSUP, THDOM(max) = 0.422×VSUP, VSUP

= 7.6 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 7-1

0.581

D3

Duty cycle 3(1) (2)

THREC(max) = 0.778×VSUP, THDOM(max) = 0.616×VSUP, VSUP

= 7.0 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 7-1

0.417

D4

Duty cycle 4(1) (2)

THREC(max) = 0.251×VSUP, THDOM(max) = 0.389×VSUP, VSUP

= 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 7-1

0.590

trx_pdr

Receiver rising propagation delay

time

RL = 2.4 kΩ, CL = 20 pF, See Figure 7-1

6

µs

trx_pdf

Receiver rising propagation delay

time

RL = 2.4 kΩ, CL = 20 pF, See Figure 7-1

6

µs

trx_sym

Symmetry of receiver propagation

delay time (rising edge)

with respect to falling edge, See Figure 7-1

–2

2

µs

tNWake

NWake filter time for local wake-up See Figure 7-1

25

50

100

µs

tLINBUS

LIN wake-up filter time (dominant

time for wake-up via LIN bus)

See Figure 7-1

25

50

100

µs

tDST

Dominant state timeout(3)

See Figure 7-1

6

9

14

ms

(1)

Duty cycle = tBUS_rec(min)/ (2×tBIT)

(2)

Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 6.8 nF, 660 Ω; Load3 = 10 nF, 500

Ω. Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is

capable of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations

from the LIN 2.0 duty cycle definitions (LIN 2.1 compatible), for details please refer to the SAEJ2602 specification.

(3)

Dominant state timeout will limit the minimum data rate to 2.4 kbps.

TPIC1021

SLIS113E – OCTOBER 2004 – REVISED MAY 2022

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