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INA260

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SBOS656C – JULY 2016 – REVISED DECEMBER 2016

Product Folder Links: INA260

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Copyright © 2016, Texas Instruments Incorporated

(1)

Conditions: Load = 12.5 A, VCM = 11.98 V.

8.5 Programming

8.5.1 Calculating Returned Values

The LSB size for the Bus Voltage Register (02h), Current Register, and Power Register are fixed and are shown

in Table 1. To calculate any of the values for current, voltage or power take the decimal value returned by the

device and multiply that value by the LSB size. For example, the LSB for the bus voltage is 1.25 mV/bit, if the

device returns a decimal value of 9584 (2570h), the value of the bus voltage is calculated to be

1.25 mV × 9584 = 11.98 V. Because the INA260 supports current measurements in either direction, the returned

value for negative currents (currents flowing from IN- to IN+) is represented in two's complement format.

Returned values for power will always be positive even when the current is negative.

Table 1. Calculating Current and Power(1)

REGISTER NAME

ADDRESS

CONTENTS

DEC

LSB

VALUE

Current Register

01h

2710h

10000

1.25 mA

12.5 A

Bus Voltage Register

02h

2570h

9584

1.25 mV

11.98 V

Power Register

03h

3A7Fh

14975

10 mW

149.75 W

8.5.2 Default Settings

The default power-up states of the registers are shown in the Register Maps section of this data sheet. These

registers are volatile, and if programmed to a value other than the default values shown in Table 4, they must be

re-programmed at every device power-up.

8.5.3 Communications Bus Overview

The INA260 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are

essentially compatible with one another.

The I2C interface is used throughout this data sheet as the primary example, with SMBus protocol specified only

when a difference between the two systems is discussed. Two lines, SCL and SDA, connect the device to the

bus. Both SCL and SDA connect to the bus and require external pullup resistors.

The device that initiates a data transfer is called a master, and the devices controlled by the master are slaves.

The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access,

and generates START and STOP conditions. The SCL pin on the INA260 is an input only and will not stretch the

clock by holding the clock line low.

To address a specific device, the master initiates a start condition by pulling the data signal line (SDA) from a

high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on the rising edge

of SCL, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the

slave being addressed responds to the master by generating an Acknowledge and pulling SDA low.

Data transfer is then initiated and eight bits of data are sent, followed by an Acknowledge bit. During data

transfer, SDA must remain stable while SCL is high. Any change in SDA while SCL is high is interpreted as a

start or stop condition.

After all data have been transferred, the master generates a stop condition, indicated by pulling SDA from low to

high while SCL is high. The device includes a 28-ms timeout on its interface to prevent locking up the bus.

8.5.3.1 Serial Bus Address

To communicate with the device, the master must first address the INA260 through a slave address byte. The

slave address byte consists of seven address bits and a direction bit that indicates whether the action is to be a

read or write operation.

The device has two address pins, A0 and A1 that can be connected to GND, VS, SCL or SDA to set the desired

address. Table 2 lists the pin connections for each of the 16 possible addresses. The device samples the state of

pins A0 and A1 on every bus communication in order to establish the pin states before any activity on the

interface occurs.