AP74502Q, AP74502HQ

Document number: DS47093 Rev. 1 - 2

2 of 22

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April 2025

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AP74502Q, AP74502HQ

, AP

Typical Applications Circuit

AP74502(H)Q

GATE

SRC

OVLO

VCAP

GND

Voltage

Regulator

(DC/DC, LDO)

TVS

Q1

CIN

COUT

CVCAP

Battery /

Power

Source

VI N

R1

R2

EN/UVLO

ON

OFF

Q2

Reverse Polarity/Overvoltage Protection with Load

Disconnect (Dual FETs)

AP74502(H)Q

GATE

SRC

OVLO

VCAP

GND

Voltage

Regulator

(DC/DC, LDO)

TVS

CIN

COUT

CVCAP

Battery /

Power

Source

VI N

EN/UVLO

ON

OFF

Reverse Polarity Protection (Single FET)

AP74502(H)Q

GATE

SRC

OVLO

VCAP

GND

Voltage

Regulator

(DC/DC, LDO)

TVS

Q1

CIN

COUT

CVCAP

Battery /

Power

Source

VI N

R1

R2

EN/UVLO

ON

OFF

Load Switch Controller with Overvotlage Protection (Single FET)

Pin Descriptions

Pin Name

Pin Number

Function

EN/UVLO

1

EN/ UVLO Control pin. Enable/ Shutdown can be controlled IO control from processor. This pin also support

UVLO feature with external resistor divider.

GND

2

Ground Pin

NC

3

No Connection

VCAP

4

Charge pump output pin. Connect external Capacitor (minimum 0.1

μF) between VIN and VCAP.

VIN

5

Input power supply to the device. Connect CIN (> 0.1

μF) between VIN and GND.

GATE

6

GATE driver output. Connect to the gate of external NMOS FET.

OVLO

7

OVLO input pin. Connect external resistor divider to adjust OVLO threshold. Connect to GND if OVLO

feature is not used.

SRC

8

Power input for gate driver. Connect to the source of external NMOS FET.

Functional Block Diagram

VCP

GATE

EN/UVLO

GND

SRC

Gate

Driver

AP74502(H)Q

CONTROL

LOGIC

Charge

Pump

EN

OVLO

VIN

OVLO

UVLO

EN

VCP

Discharge

Discharge

Discharge