ADC31RF80 datasheet(56/142 Pages) TI2

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SYNCb

SYSREF

LMFC Clock

LMFC Boundary

xxx

Transmit Data

K28.5

ILA

DATA

Multi

Frame

Code Group

Synchronization

Initial Lane Alignment

Data Transmission

ADC31RF80

SBAS860 – AUGUST 2017

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Device Functional Modes (continued)

8.4.2.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB

signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected

on the SYNCB input, as shown in Figure 133, the ADC31RF80 starts transmitting comma (K28.5) characters to

establish the code group synchronization.

When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC31RF80 starts

the initial lane alignment sequence with the next local multiframe clock boundary. The ADC31RF80 transmits

four multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame

start and end symbols. The second multiframe also contains the JESD204 link configuration data.

Figure 133. JESD Internal Timing Information

8.4.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

•

F is the number of octets per frame clock period

•

L is the number of lanes per link

•

M is the number of converters for the device

•

S is the number of samples per frame

ADC31RF80 Datasheet(PDF) 56 Page - Texas Instruments