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DS250DF230ZLS Datasheet(PDF) 39 Page - Texas Instruments |
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DS250DF230ZLS Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 119 page  Table 8-10. Channel Registers, 0 to 39 ADDRESS (HEX) BITS DEFAULT VALUE (HEX) MODE EEPROM FIELD NAME DESCRIPTION 00 7 0 RW N RESERVED RESERVED 6 0 RW N RESERVED RESERVED 5 0 RW N RESERVED RESERVED 4 0 RW N RESERVED RESERVED 3 0 RW N RST_CORE 1: Reset the 10M core clock domain. This is the main clock domain for all the state machines 0: Normal operation 2 0 RW N RST_REGS 1: Reset channel registers to power-up defaults. 0: Normal operation 1 0 RW N RST_VCO 1: Resets the CDR S2P clock domain, includes PPM counter, EOM counter. 0: Normal operation 0 0 RW N RST_REFCLK 1: Resets the 25MHz reference clock domain, includes PPM counter. Does not work if 25MHz clock is not present. 0: Normal operation 01 7 0 R N SIGDET Raw Signal Detect observation 6 0 R N POL_INV_DET Indicates PRBS checker detected polarity inversion in the locked data sequence. 5 0 R N CDR_LOCK_LOSS_INT 1: Indicates loss of CDR lock after having acquired it. Bit clears on read. Feature must be enabled with Reg_0x31[1] 4 0 R N PRBS_SEQ_DET[3] Indicates the pattern detected on the input serial stream 0xxx: No detect 1000: 7 bits PRBS sequence 1001: 9 bits PRBS sequence 1010: 11 bits PRBS sequence 1011: 15 bits PRBS sequence 1100: 23 bits PRBS sequence 1101: 31 bits PRBS sequence 1110: 58 bits PRBS sequence 1111: 63 bits PRBS sequence 3 0 R N PRBS_SEQ_DET[2] 2 0 R N PRBS_SEQ_DET[1] 1 0 R N PRBS_SEQ_DET[0] 0 0 R N SIG_DET_LOSS_INT Loss of signal indicator, set once signal is acquired and then lost. Clears on read. Feature must be enabled with reg_31[0] www.ti.com DS250DF230 SNLS590C – AUGUST 2018 – REVISED JUNE 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DS250DF230 |
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