DS250DF230ZLS datasheet(13/119 Pages) TI2

13 / 119 page

7.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CLKODC

Intrinsic calibration clock duty

cycle distortion

Intrinsic duty cycle distortion of

chip calibration clock output at the

CAL_CLK_OUT pin, assuming 50% duty

cycle on CAL_CLK_IN pin.

55 Percent

CLKnum

Number of devices which can be

cascaded from CAL_CLK_OUT to

CAL_CLK_IN

Assumes worst-case 60%/40% input duty

cycle on the first device. CAL_CLK_OUT

from first device connects to CAL_CLK_IN

of second device, and so on until the last

device.

N/A

LVCMOS DC SPECIFICATIONS

VIH

Input high-level voltage

2.5 V LVCMOS pins

1.75

VDD

3.3 V LVCMOS pin (READ_EN_N)

1.75

3.6

VIL

Input low-level voltage

2.5 V LVCMOS pins

GND

0.7

3.3 V LVCMOS pin (READ_EN_N)

GND

0.8

Vth

High-level(1) input voltage

4-level pins ADDR0, ADDR1, EN_SMB

and THR

0.98 x VDD

Float level input voltage

4-level pins ADDR0, ADDR1, EN_SMB

and THR

0.69 x VDD

10K to GND input voltage

4-level pins ADDR0, ADDR1, EN_SMB

and THR

0.25 x VDD

Low-level (0) input voltage

4-level pins ADDR0, ADDR1, EN_SMB

and THR

0.1

VOH

High-level output voltage

IOH = 4mA

VOL

Low-level output voltage

IOL = -4mA

0.4

IIH

Input high leakage current

Vinput = VDD, Open drain pins

Input high leakage current

Vinput = VDD and CAL_CLK_IN pins

Input high leakage current

Vinput = VDD, ADDR[1:0] and EN_SMB

pins

Input high leakage current

Vinput = VDD, READ_EN_N

IIL

Input low leakage current

Vinput = 0V, Open drain pins

–15

Input low leakage current

Vinput = 0V, CAL_CLK_IN pins

–15

Input low leakage current

Vinput = 0V, ADDR[1:0], READ_EN_N, and

EN_SMB pins

–115

(1)

From low assertion of READ_EN_N to low_assertion of ALL_DONE_N. Does not include Power-On Reset time

(2)

Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9

GHz between DS250DF230 and the measurement instrument.

(3)

Prior to EQ adaptation completion, retimer output may not be error-free.

(4)

There may be an observed increase from the typical tEQ_Adapt time for lower line rates (e.g. 10.3125 Gbps).

(5)

Measured with an evaluation board which uses microstrip traces and low-loss dielectric with approximately 4 dB insertion loss at 12.9

GHz between DS250DF230 and the measurement instrument.

(6)

Measured with input data from DS280DF810 evaluation board, at 24.33024 Gbps or 10.1376 Gbps or 25.78125Gbps or 10.3125

Gbps.

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DS250DF230

SNLS590C – AUGUST 2018 – REVISED JUNE 2021

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