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DS250DF230ZLS Datasheet(PDF) 4 Page - Texas Instruments |
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DS250DF230ZLS Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 119 page  6 Pin Configuration and Functions TX0P TX0N GND GND TX1P TX1N GND GND READ_EN _N ALL_DONE _N GND GND CAL_CLK _IN THR/TEST1 VDD VDD SDA CAL_CLK _OUT EN_SMB TEST0/ RCK0 VDD VDD SDC ADDR0 GND GND ADDR1 INT_N GND GND RX0P RX0N GND GND RX1P RX1N F E D C B A F E D C B A 6 5 4 3 2 1 6 5 4 3 2 1 Legend Control/Status High-Spe ed Gro und Power Figure 6-1. ZLS Package 36-Pin NFBGA Top View 1 2 3 5 6 4 Thermal Pad (DAP) 7 8 13 14 12 9 10 11 15 16 24 23 22 20 19 21 18 17 28 27 29 32 31 30 26 25 ALL_DONE_N VDD VDD INT_N ADDR0 SDC SDA CAL_CLK_IN READ_EN_N VDD THR/TEST1 TEST0/RCK0 VDD EN_SMB ADDR1 CAL_CLK_OUT Figure 6-2. RTV Package 32-Pin QFN Top View Table 6-1. Pin Functions PIN TYPE INTERNAL PULL-UP/ PULL- DOWN DESCRIPTION NAME NFBGA QFN HIGH-SPEED DIFFERENTIAL I/Os RX0P A6 18 Input None Inverting and noninverting differential inputs to the equalizer. An on- chip, 100-Ω termination resistor connects RXP to RXN. These inputs must be AC-coupled. RX0N A5 19 Input None RX1P A2 22 Input None Inverting and noninverting differential inputs to the equalizer. An on- chip, 100-Ω termination resistor connects RXP to RXN. These inputs must be AC-coupled. RX1N A1 23 Input None TX0P F6 7 Output None Inverting and noninverting 50Ω driver outputs. These outputs must be AC-coupled. TX0N F5 6 Output None TX1P F2 3 Output None Inverting and noninverting 50Ω driver outputs. These outputs must be AC-coupled. TX1N F1 2 Output None CALIBRATION CLOCK PINS CAL_CLK_IN D6 10 Input, 2.5V LVCMOS None 30.72-MHz (±100 PPM), 2.5-V single-ended clock from external oscillator. No stringent phase noise or jitter requirements on this clock. Also supports 25-MHz (±100 PPM) clock by programming the corresponding registers. CAL_CLK_OUT D1 31 Output, 2.5V LVCMOS None 2.5-V buffered replica of calibration clock input (CAL_CLK_IN) for connecting multiple (up to 20 or more) devices in a daisy-chained fashion. SYSTEM MANAGEMENT BUS (SMBus) PINS ADDR0 C1 25 Input, 4-level None 4-level strap pins used to set the SMBus address of the device. The pin state is read on power-up. The multi-level nature of these pins allows for 16 unique device addresses. The four strap options include: 0: 1 kΩ to GND R: 10 kΩ to GND F: Float 1: 1 kΩ to VDD Refer to Section 8.4.3 for more information. ADDR1 B4 16 Input, 4-level None DS250DF230 SNLS590C – AUGUST 2018 – REVISED JUNE 2021 www.ti.com 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: DS250DF230 |
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