L9965TS datasheet(48/62 Pages) STMICROELECTRONICS

48 / 62 page

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Diagnosis related to SPI or VIF communication events: ISO_ERR, FIFO_RX_EMPTY, FIFO_RX_FULL,

FIFO_TX_FULL, WAKEUP_FAULT_VIF, SPI_VIF_ID_ERR, SPI_COMM_CRC_ERR,

SPI_WRONG_ADDR, SPI_SHORT_FRAME, SPI_LONG_FRAM, ISO_COMM_CRC_ERR,

ISO_SHORT_FRAME, ISO_LONG_FRAME. In this case the status bits are always cleared by sw reset.

To reset the device configuration, the following procedure shall be implemented.

Procedure 4: Software reset

1. Write 0xE1 in the SPECIAL_REG register to enter in partial reset mode

2. Write 0x1E in the SPECIAL_REG register to confirm the reset

3. If required from the application, download the configuration from the NVM.

Since the NVM is re-downloaded at each wakeup, any new configuration should be pushed into the memory with

a “write” instruction (see Section 5.12.1). Otherwise, the previous configuration will be restored at the next

wakeup event.

5.12

Non-Volatile Memory (NVM)

Key device Device key configuration parameters can be stored in the internal NVM. For the registers that can be

saved to the NVM please refer to the device register map.

5.12.1

NVM Read/Write Operations

NVM data is automatically downloaded into local registers every time that the IC performs the following FSM

transitions:

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DEEP SLEEP to NORMAL

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CYCLIC_COUNT to CYCLIC_WAKEUP

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CYCLIC_COUNT to NORMAL

When the IC performs FSM transitions to DEEPSLEEP or CYCLIC_COUNT state, a selected group of data stored

in local registers is retained to guarantee IC correct operation (VIF_ID_CFG, GEN_CFG1, GEN_CFG2,

GEN_CFG3), while all other data is lost. Such data will be re-downloaded in next transition to NORMAL.

When the IC performs FSM transitions to OFF state, all data stored in local registers is lost; NVM data will be re-

downloaded in next transition to NORMAL.

As the IC reaches NORMAL state, the following commands allow user interaction with the NVM:

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GENERAL_REG.VM_OP_CMD=0x3 triggers the NVM upload and refresh: this operation fetches the data

previously written into configuration registers and writes it to the relative NVM sectors, then it automatically

triggers a full NVM re-download to guarantee whole data consistency. The operation lasts TNVM_UPLOAD

and during such time interval the MCU will not be able to perform R/W operations (any command will be

discarded)

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GENERAL_REG.NVM_OP_CMD=0x5 triggers the NVM refresh, fetching the data from NVM sectors and

writing it to the configuration registers. The operation lasts TNVM_DOWNLOAD and during such time interval

the MCU will not be able to perform R/W operations (any command will be discarded)

During NVM upload/download operations, GENERAL_REG.NVM_READY bit is reset to ‘0’, indicating that NVM is

busy. Once the task is complete, the GENERAL_REG.NVM_READY is set; as no NVM read/write operation is

running, the NVM circuit is kept under reset.

To guarantee data retention, NVM write operation number must not exceed NNVM_WRITE_CYCLES; if such a limit is

exceeded, data retention is not guaranteed. The IC continues to accept and perform every write operation, even if

it is beyond NNVM_WRITE_CYCLES count. Every time a write operation is performed, the IC automatically updates

the GEN_CFG1.NVM_UPLOAD_COUNT counter field, stored in the NVM as well. The counter value saturates at

NNVM_WRITE_CYCLES: if a new write operation is done above the NNVM_WRITE_CYCLES limit, counter value is

increased at NNVM_WRITE_CYCLES+1 and will never be updated anymore.

5.12.2

NVM data integrity checks

Device trimming data and configuration data (used to configure IC operation) in VIF_ID_CFG, GEN_CFG1,

GEN_CFG2, GEN_CFG3 registers are stored in different sectors, each protected by its own CRC.

Every time the IC performs an NVM download operation (either automatic or user-driven), an integrity check of

the NVM CRC (sector by sector) is performed.

Every time the user triggers an NVM upload and refresh operation, the corresponding sector CRC is updated as

well; this is done by IC automatically.

L9965T/L9965TS

Functional description

DS14987 - Rev 1

page 48/62

L9965TS Datasheet(PDF) 48 Page - STMicroelectronics

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