L9965TS datasheet(38/62 Pages) STMICROELECTRONICS

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2. Setting the CMD_TRX field in CMD_REG equal to 0xB5. This is a dedicated read command that must be sent

for all the FIFO locations to read. The command doesn’t transfer any data on the VIF interface.

3. With an SPI burst access approach to reduce the time needed to readout long data series from a single unit.

This access is achieved by MCU asserting the NCS and sending N*40 clock cycles on SCK, where N is the

number of frames to be read from FIFO. If a wrong number of clock cycle is sent by MCU, the last frame is not

reliable and the pointed FIFO location is lost. At the next access to the SPI slave, an SPI ERROR frame is

sent, and an error bit (SPI_SHORT_FRAME or SPI_LONG_FRAME) is asserted in the status register

COMM_ERR_SPI.

Figure 13. SPI burst read

5.8.2.5

RX VIF FIFO handling

The device includes two types of memory: the internal register memory, which configures the device

functionalities, and the VIF RX FIFO, which stores all frames received from the Vertical Interface. Access to these

memories is managed using a hardware pointer. This pointer changes based on the SPI request received and

points to the register whose value will be shifted out on the next MISO.

•

When the MCU sends an SPI read/write command addressing the IC's own registers, the pointer switches

to the internal register map at the end of the SPI frame.

•

When the MCU sends an SPI read/write command to pop a VIF frame from the FIFO, the pointer switches

to the FIFO at the end of the SPI frame.

•

When the MCU sends an SPI read/write command addressing an external device on the VIF bus, the

pointer switches to the FIFO at the end of the SPI frame.

The pointer's behavior is transparent when the MCU retrieves VIF data from the same transceiver used to send

the VIF request. However, it becomes visible when the MCU sends a VIF request from one transceiver and

retrieves the response from the opposite transceiver.

Referring to Figure 14, in a dual-ring topology with the bidirectional answer enabled for all devices, the MCU

reads an internal register of the high transceiver during time interval [t0-t1]. Then it sends a standard burst

command to a device along the chain from the low transceiver during time interval [t2-t3-t4].

To read the response frames from the same transceiver side, the MCU must send N FIFO POP commands during

time interval [t5-t6-…], where N is the number of burst response frames. If the MCU needs to read the responses

using the high transceiver, it must send N+2 FIFO POP commands. The first retrieves the internal register data

(requested initially) and updates the pointer to the first FIFO location [t5]. The second retrieves the burst request

(sent by the low transceiver) [t6], and the remaining N FIFO POP commands retrieve the burst answers during

time interval [t7-t8-…].

L9965T/L9965TS

Functional description

DS14987 - Rev 1

page 38/62

L9965TS Datasheet(PDF) 38 Page - STMicroelectronics