6.5 Electrical Characteristics (continued)

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at TA = 25°C, VREF = VS/2, G = 10, RL = 10 kΩ connected to VS / 2,

VCM = [(VIN+) + (VIN–)] / 2 = VS / 2, VIN = (VIN+) – (VIN–) = 0 V and VOUT = VS / 2 (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tS

Settling time

G = 10, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

14

µs

G = 10, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

24

G = 20, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

20

G = 20, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

30

Settling time

G = 30, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

30

G = 30, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

40

G = 50, To 0.1%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

45

G = 50, To 0.01%, VS = 5.5 V, VSTEP = 2 V, CL = 10 pF

55

Overload recovery

VIN = 1 V, G = 10

8

µs

REFERENCE BUFFER

REF -

VIN

Linear input voltage range VS = 5.5 V

(V–) + 0.1

(V+) – 0.1

V

REF - G Reference gain to output

1

V/V

REF -

GE

Reference gain error(4)

VS = 5.5 V

±0.015

±0.10

%

REF -

ZIN

Input impedance

VS = 5.5 V

100 || 5

GΩ || pF

REF - IB Reference pin bias current VS = 5.5 V

±0.65

pA

POWER SUPPLY

VS

Power-supply voltage

Single-supply

1.7

5.5

V

Dual-supply

±0.85

±2.75

IQ

Quiescent current

VIN = 0 V

110

135

µA

TA = –40°C to 125°C

147

IQSD

Quiescent current per

amplifier

All amplifiers disabled, SHDN = V–

0.85

1.5

µA

VIL

Logic low threshold

voltage (Gain Select)

G = 10 for INA351ABS, G = 30 for INA351CDS

(V–) + 0.2 V

V

VIH

Logic high threshold

voltage (Gain Select)

G = 20 for INA351ABS, G = 50 for INA351CDS

(V–) + 1 V

V

tON

Amplifier enable time (full

shutdown) (6)

G = 10, VCM = VS / 2, VO = 0.9 × VS / 2,

RL connected to V–

100

µs

tOFF

Amplifier disable time (6)

G = 10, VCM = VS / 2, VO = 0.1 × VS / 2,

RL connected to V–

5

µs

SHDN pin input bias

current (per pin)

(V+) ≥ SHDN ≥ (V–) + 1 V

10

nA

SHDN pin input bias

current (per pin)

(V–) ≤ SHDN ≤ (V–) + 0.2 V

175

nA

(1)

Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).

(2)

Offset drifts are uncorrelated. Input-referred offset drift is calculated using: ΔVOS(RTI) = √[ΔVOSI 2 + (ΔVOSO / G)2]

(3)

Input common-mode voltage range of the just the input stage of the instrumentation amplifier. The entire INA351 input range depends

on the combination input common-mode voltage, differential voltage, gain, reference voltage and power supply voltage. Typical

Characteristic curves will be added with more information.

(4)

Minimum and Maximum values are specified by characterization.

(5)

Total RTI voltage noise is equal to: eN(RTI) = √[eNI 2 + (eNO / G)2]

(6)

Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

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INA351

SBOSAD5D – DECEMBER 2022 – REVISED NOVEMBER 2024

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