8.3 Power Supply Recommendations

The LMC555 requires a voltage supply within 1.5 V to 15 V. Adequate power supply bypassing is necessary

to protect associated circuitry; the minimum recommended is 0.1 μF in parallel with 1-μF electrolytic. Place the

bypass capacitors as close as possible to the LMC555 and minimize the trace length.

8.4 Layout

8.4.1 Layout Guidelines

Standard PCB rules apply to routing the LMC555. Keep the 0.1 µF capacitor in parallel with a 1-µF electrolytic

capacitor as close as possible to the LMC555. Place the capacitor used for the time delay as close as possible

to the DISCHARGE pin. Use a ground plane on the bottom layer to provide better noise immunity and signal

integrity.

8.4.2 Layout Example

The figure below is the basic layout for various applications.

• C1 – based on time delay calculations

• C2 – 0.01 µF bypass capacitor for control voltage pin

• C3 – 0.1 µF bypass ceramic capacitor

• C4 – 1-µF electrolytic bypass capacitor

• R1 – based on time delay calculations

• U1 – LMC555

C

4

V+

C

3

R

1

C

1

C

2

CONTROL

VOLTAGE

GND

8

7

6

5

1

2

3

4

OUTPUT

TRIGGER

RESET

GND

If reset feature is not

used, connect

RESET to V+

GND

Figure 8-10. PCB Layout

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LMC555

SNAS558N – JANUARY 2000 – REVISED MARCH 2024

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