LMX2572LP datasheet(3/83 Pages) TI2

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RampClk

GND

VrefVCO2

VbiasVCO

SysRefReq

GND

VbiasVCO2

SYNC

VccVCO2

GND

VccDIG

CSB

OSCinP

RFoutAP

OSCinM

RFoutAM

VregIN

VccBUF

Not to scale

DAP

LMX2572LP

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SNAS764 – MAY 2018

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5 Pin Configuration and Functions

RHA Package

40-Pin VQFN

Top View

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Input

Chip enable. High impedance CMOS input. 1.8-V to 3.3-V logic. Active HIGH powers on the

device.

CPout

Output

Charge pump output. Place C1 of loop filter close to this pin.

CSB

Input

SPI latch. High impedance CMOS input. 1.8-V to 3.3-V logic.

DAP

—

Ground

RF ground.

GND

2, 4, 25, 31,

34, 39

Ground

VCO ground.

6, 14, 40

Ground

Digital ground.

Ground

Charge pump ground.

MUXout

Output

Multiplexed output pin. Configurable between lock detect and register readback.

OSCinM

Input

Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling.

OSCinP

Input

Reference input clock (+). High impedance self-biasing pin. Requires AC-coupling.

RampClk

Input

Ramp trigger in automatic ramping mode or ramp clock in manual ramping mode. Can also

be used as FSK I2S clock input. High impedance CMOS input. 1.8-V to 3.3-V logic.

RampDir

Input

Ramp trigger in automatic ramping mode or ramp segment selection in manual ramping

mode. Can also be used as FSK I2S data input. High impedance CMOS input. 1.8-V to 3.3-V

logic.

RFoutAM

Output

Differential output A (–). Low impedance output. Requires AC-coupling.

RFoutAP

Output

Differential output A (+). Low impedance output. Requires AC-coupling.

RFoutBM

Output

Differential output B (–). Low impedance output. Requires AC-coupling.

RFoutBP

Output

Differential output B (+). Low impedance output. Requires AC-coupling.

SCK

Input

SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic.

LMX2572LP Datasheet(PDF) 3 Page - Texas Instruments

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