PCM1795DB datasheet(32/68 Pages) TI2

32 / 68 page

PCM1795

SLES248A – MAY 2009 – REVISED MARCH 2015

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7.6.1.3.11

ATS[1:0]: Attenuation Rate Select

These bits are available for read and write.

Default value: 00

Table 18. ATS[1:0]

ATS[1:0]

ATTENUATION RATE SELECTION

Every LRCK (default)

LRCK/2

LRCK/4

LRCK/8

The ATS[1:0] bits are used to select the rate at which the attenuator is decremented/incremented during level

transitions.

7.6.1.3.12

OPE: DAC Operation Control

This bit is available for read and write.

Default value: 0

Table 19. OPE

OPE

DAC OPERATION CONTROL

OPE = 0

DAC operation enabled (default)

OPE = 1

DAC operation disabled

The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs

forces them to the bipolar zero level (BPZ) even if audio data are present on the input.

7.6.1.3.13

DFMS: Stereo DF Bypass Mode Select

This bit is available for read and write.

Default value: 0

Table 20. DFMS

DFMS

MODE SELECTION

DFMS = 0

Monaural (default)

DFMS = 1

Stereo input enabled

The DFMS bit is used to enable stereo operation in DF bypass mode. In the DF bypass mode, when DFMS is

set to '0', the pin for the input data are DATA (pin 5) only; therefore, the PCM1795 operates as a monaural DAC.

When DFMS is set to '1', the PCM1795 can operate as a stereo DAC with inputs of the left channel and right

channel data on ZEROL (pin 1) and ZEROR (pin 2), respectively.

7.6.1.3.14

FLT: Digital Filter Roll-Off Control

This bit is available for read and write.

Default value: 0

Table 21. FLT

FLT

ROLL-OFF CONTROL

FLT = 0

Sharp roll-off (default)

FLT = 1

Slow roll-off

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